hdmirx_writel
hdmirx_writel(hdmirx_dev, DMA_CONFIG2,
hdmirx_writel(hdmirx_dev, DMA_CONFIG3,
hdmirx_writel(hdmirx_dev, DMA_CONFIG5, 0xffffffff);
hdmirx_writel(hdmirx_dev, CED_DYN_CONTROL, 0x1);
hdmirx_writel(hdmirx_dev, AVPUNIT_0_INT_FORCE, 0x0);
hdmirx_writel(hdmirx_dev, MAINUNIT_0_INT_FORCE, 0x0);
hdmirx_writel(hdmirx_dev, MAINUNIT_2_INT_FORCE, 0x0);
hdmirx_writel(hdmirx_dev, DMA_CONFIG2,
hdmirx_writel(hdmirx_dev, DMA_CONFIG3,
hdmirx_writel(hdmirx_dev, DMA_CONFIG5, 0xffffffff);
hdmirx_writel(hdmirx_dev, DMA_CONFIG5, 0xffffffff);
hdmirx_writel(hdmirx_dev, GLOBAL_SWRESET_REQUEST, DATAPATH_SWRESETREQ);
.write = hdmirx_writel,
hdmirx_writel(hdmirx_dev, MAINUNIT_0_INT_MASK_N, 0);
hdmirx_writel(hdmirx_dev, MAINUNIT_1_INT_MASK_N, 0);
hdmirx_writel(hdmirx_dev, MAINUNIT_2_INT_MASK_N, 0);
hdmirx_writel(hdmirx_dev, AVPUNIT_0_INT_MASK_N, 0);
hdmirx_writel(hdmirx_dev, AVPUNIT_1_INT_MASK_N, 0);
hdmirx_writel(hdmirx_dev, PKT_0_INT_MASK_N, 0);
hdmirx_writel(hdmirx_dev, PKT_1_INT_MASK_N, 0);
hdmirx_writel(hdmirx_dev, PKT_2_INT_MASK_N, 0);
hdmirx_writel(hdmirx_dev, SCDC_INT_MASK_N, 0);
hdmirx_writel(hdmirx_dev, CEC_INT_MASK_N, 0);
hdmirx_writel(hdmirx_dev, PHYCREG_CONFIG0, 0x3);
hdmirx_writel(hdmirx_dev, CORE_CONFIG,
hdmirx_writel(hdmirx_dev, DMA_CONFIG10, edid[i]);
hdmirx_writel(hdmirx_dev, reg, val);
hdmirx_writel(hdmirx_dev, MAINUNIT_0_INT_MASK_N, 0);
hdmirx_writel(hdmirx_dev, MAINUNIT_2_INT_MASK_N, 0);
hdmirx_writel(hdmirx_dev, AVPUNIT_0_INT_MASK_N, 0);
hdmirx_writel(hdmirx_dev, PHYCREG_CONFIG0, 0x0);
hdmirx_writel(hdmirx_dev, PHYCREG_CONFIG1, phy_reg);
hdmirx_writel(hdmirx_dev, PHYCREG_CONTROL, PHYCREG_CR_PARA_READ_P);
hdmirx_writel(hdmirx_dev, PHYCREG_CONFIG1, phy_reg);
hdmirx_writel(hdmirx_dev, PHYCREG_CONFIG2, val);
hdmirx_writel(hdmirx_dev, PHYCREG_CONTROL, PHYCREG_CR_PARA_WRITE_P);
hdmirx_writel(hdmirx_dev, PHYCREG_CONFIG0, 0x3);
hdmirx_writel(hdmirx_dev, GLOBAL_TIMER_REF_BASE, iref_clk_freq_hz);