hdmirx_readl
val = hdmirx_readl(hdmirx_dev, DMA_STATUS11);
val = hdmirx_readl(hdmirx_dev, PKTDEC_AVIIF_PH2_1);
val = hdmirx_readl(hdmirx_dev, PKTDEC_AVIIF_PB3_0 + 4 * i);
dma_cfg1 = hdmirx_readl(hdmirx_dev, DMA_CONFIG1);
dma_cfg1 = hdmirx_readl(hdmirx_dev, DMA_CONFIG1);
mu0_mask = hdmirx_readl(hdmirx_dev, MAINUNIT_0_INT_MASK_N);
mu2_mask = hdmirx_readl(hdmirx_dev, MAINUNIT_2_INT_MASK_N);
pk2_mask = hdmirx_readl(hdmirx_dev, PKT_2_INT_MASK_N);
scdc_mask = hdmirx_readl(hdmirx_dev, SCDC_INT_MASK_N);
mu0_st = hdmirx_readl(hdmirx_dev, MAINUNIT_0_INT_STATUS);
mu2_st = hdmirx_readl(hdmirx_dev, MAINUNIT_2_INT_STATUS);
pk2_st = hdmirx_readl(hdmirx_dev, PKT_2_INT_STATUS);
scdc_st = hdmirx_readl(hdmirx_dev, SCDC_INT_STATUS);
avp0_st = hdmirx_readl(hdmirx_dev, AVPUNIT_0_INT_STATUS);
avp1_st = hdmirx_readl(hdmirx_dev, AVPUNIT_1_INT_STATUS);
avp0_msk = hdmirx_readl(hdmirx_dev, AVPUNIT_0_INT_MASK_N);
avp1_msk = hdmirx_readl(hdmirx_dev, AVPUNIT_1_INT_MASK_N);
dma_cfg6 = hdmirx_readl(hdmirx_dev, DMA_CONFIG6);
dma_stat1 = hdmirx_readl(hdmirx_dev, DMA_STATUS1);
dma_stat13 = hdmirx_readl(hdmirx_dev, DMA_STATUS13);
mu_status = hdmirx_readl(hdmirx_dev, MAINUNIT_STATUS);
scdc_status = hdmirx_readl(hdmirx_dev, SCDC_REGBANK_STATUS3);
dma_st10 = hdmirx_readl(hdmirx_dev, DMA_STATUS10);
cmu_st = hdmirx_readl(hdmirx_dev, CMU_STATUS);
.read = hdmirx_readl,
mu_status = hdmirx_readl(hdmirx_dev, MAINUNIT_STATUS);
dma_st10 = hdmirx_readl(hdmirx_dev, DMA_STATUS10);
cmu_st = hdmirx_readl(hdmirx_dev, CMU_STATUS);
val = hdmirx_readl(hdmirx_dev, DMA_STATUS2);
val = hdmirx_readl(hdmirx_dev, DMA_STATUS3);
val = hdmirx_readl(hdmirx_dev, DMA_STATUS4);
val = hdmirx_readl(hdmirx_dev, DMA_STATUS5);
u32 val = hdmirx_readl(hdmirx_dev, DMA_CONFIG6);
val = hdmirx_readl(hdmirx_dev, DMA_STATUS11);
deframer_st = hdmirx_readl(hdmirx_dev, DEFRAMER_STATUS);
tmdsqpclk_freq = hdmirx_readl(hdmirx_dev, CMU_TMDSQPCLK_FREQ);
data[i] = hdmirx_readl(hdmirx_dev, DMA_STATUS14);
hdmirx_readl(hdmirx_dev, reg - 0x8);
val = hdmirx_readl(hdmirx_dev, reg);
status = hdmirx_readl(hdmirx_dev, PHYCREG_STATUS);
val = hdmirx_readl(hdmirx_dev, SCDC_REGBANK_STATUS1);
val = hdmirx_readl(hdmirx_dev, DMA_STATUS11);