hdmi_wp_data
struct hdmi_wp_data *wp;
struct hdmi_wp_data *wp;
int hdmi_wp_video_start(struct hdmi_wp_data *wp);
void hdmi_wp_video_stop(struct hdmi_wp_data *wp);
void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s);
u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp);
void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus);
void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask);
void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask);
int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val);
int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val);
void hdmi_wp_video_config_format(struct hdmi_wp_data *wp,
void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp,
void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp,
int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp,
phys_addr_t hdmi_wp_get_audio_dma_addr(struct hdmi_wp_data *wp);
struct hdmi_pll_data *pll, struct hdmi_wp_data *wp);
int hdmi_wp_audio_enable(struct hdmi_wp_data *wp, bool enable);
int hdmi_wp_audio_core_req_enable(struct hdmi_wp_data *wp, bool enable);
void hdmi_wp_audio_config_format(struct hdmi_wp_data *wp,
void hdmi_wp_audio_config_dma(struct hdmi_wp_data *wp,
struct hdmi_wp_data wp;
struct hdmi_wp_data *wp = &hdmi->wp;
struct hdmi_wp_data *wp = &hdmi->wp;
struct hdmi_wp_data *wp)
struct hdmi_wp_data;
struct hdmi_wp_data *wp);
struct hdmi_wp_data *wp)
struct hdmi_wp_data *wp, struct hdmi_config *cfg)
int hdmi4_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
int hdmi4_audio_start(struct hdmi_core_data *core, struct hdmi_wp_data *wp)
void hdmi4_audio_stop(struct hdmi_core_data *core, struct hdmi_wp_data *wp)
void hdmi4_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
int hdmi4_audio_start(struct hdmi_core_data *core, struct hdmi_wp_data *wp);
void hdmi4_audio_stop(struct hdmi_core_data *core, struct hdmi_wp_data *wp);
int hdmi4_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
struct hdmi_wp_data *wp = &hdmi->wp;
void hdmi5_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
int hdmi5_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
void hdmi5_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
int hdmi5_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
struct hdmi_pll_data *pll, struct hdmi_wp_data *wp)
struct hdmi_wp_data *wp = pll->wp;
struct hdmi_wp_data *wp = pll->wp;
int hdmi_wp_video_start(struct hdmi_wp_data *wp)
void hdmi_wp_video_stop(struct hdmi_wp_data *wp)
void hdmi_wp_video_config_format(struct hdmi_wp_data *wp,
void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp,
void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp,
void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s)
void hdmi_wp_audio_config_format(struct hdmi_wp_data *wp,
void hdmi_wp_audio_config_dma(struct hdmi_wp_data *wp,
int hdmi_wp_audio_enable(struct hdmi_wp_data *wp, bool enable)
int hdmi_wp_audio_core_req_enable(struct hdmi_wp_data *wp, bool enable)
int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp,
phys_addr_t hdmi_wp_get_audio_dma_addr(struct hdmi_wp_data *wp)
u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp)
void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus)
void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask)
void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask)
int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val)
int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val)
struct hdmi_wp_data *wp;
int hdmi_wp_video_start(struct hdmi_wp_data *wp);
void hdmi_wp_video_stop(struct hdmi_wp_data *wp);
void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s);
u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp);
void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus);
void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask);
void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask);
int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val);
int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val);
void hdmi_wp_video_config_format(struct hdmi_wp_data *wp,
void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp,
void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp,
int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp);
phys_addr_t hdmi_wp_get_audio_dma_addr(struct hdmi_wp_data *wp);
struct hdmi_wp_data *wp);
int hdmi_wp_audio_enable(struct hdmi_wp_data *wp, bool enable);
int hdmi_wp_audio_core_req_enable(struct hdmi_wp_data *wp, bool enable);
void hdmi_wp_audio_config_format(struct hdmi_wp_data *wp,
void hdmi_wp_audio_config_dma(struct hdmi_wp_data *wp,
struct hdmi_wp_data wp;
struct hdmi_wp_data *wp = &hdmi.wp;
struct hdmi_wp_data *wp = data;
struct hdmi_wp_data *wp, struct hdmi_config *cfg)
int hdmi4_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
int hdmi4_audio_start(struct hdmi_core_data *core, struct hdmi_wp_data *wp)
void hdmi4_audio_stop(struct hdmi_core_data *core, struct hdmi_wp_data *wp)
void hdmi4_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
int hdmi4_audio_start(struct hdmi_core_data *core, struct hdmi_wp_data *wp);
void hdmi4_audio_stop(struct hdmi_core_data *core, struct hdmi_wp_data *wp);
int hdmi4_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
struct hdmi_wp_data *wp = data;
void hdmi5_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
int hdmi5_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
void hdmi5_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
int hdmi5_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
struct hdmi_wp_data *wp = pll->wp;
struct hdmi_wp_data *wp = pll->wp;
struct hdmi_wp_data *wp)
int hdmi_wp_video_start(struct hdmi_wp_data *wp)
void hdmi_wp_video_stop(struct hdmi_wp_data *wp)
void hdmi_wp_video_config_format(struct hdmi_wp_data *wp,
void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp,
void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp,
void hdmi_wp_audio_config_format(struct hdmi_wp_data *wp,
void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s)
void hdmi_wp_audio_config_dma(struct hdmi_wp_data *wp,
int hdmi_wp_audio_enable(struct hdmi_wp_data *wp, bool enable)
int hdmi_wp_audio_core_req_enable(struct hdmi_wp_data *wp, bool enable)
int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp)
phys_addr_t hdmi_wp_get_audio_dma_addr(struct hdmi_wp_data *wp)
u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp)
void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus)
void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask)
void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask)
int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val)
int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val)