hdmi_read_reg
hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\
FLD_GET(hdmi_read_reg(base, idx), start, end)
u32 intr4 = hdmi_read_reg(hdmi->core.base, HDMI_CORE_SYS_INTR4);
u32 stat1 = hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_1);
u32 dbg3 = hdmi_read_reg(core->base, HDMI_CEC_DBG_3);
temp = hdmi_read_reg(core->base, HDMI_CEC_DBG_3);
temp = hdmi_read_reg(core->base, HDMI_CEC_RX_CONTROL);
hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_1));
hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_0));
temp = hdmi_read_reg(core->base, HDMI_CEC_SETUP);
temp = hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_1);
v = hdmi_read_reg(core->base, HDMI_CEC_CA_7_0);
v = hdmi_read_reg(core->base, HDMI_CEC_CA_15_8);
u32 cnt = hdmi_read_reg(core->base, HDMI_CEC_RX_COUNT) & 0xff;
msg.msg[0] = hdmi_read_reg(core->base,
msg.msg[1] = hdmi_read_reg(core->base,
hdmi_read_reg(core->base, reg);
while (hdmi_read_reg(core->base, HDMI_CEC_RX_CONTROL) & 1)
cnt = hdmi_read_reg(core->base, HDMI_CEC_RX_COUNT) & 0xff;
u32 stat0 = hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_0);
r = hdmi_read_reg(core_sys_base, HDMI_CORE_SYS_SYS_CTRL1);
r = hdmi_read_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE);
r = hdmi_read_reg(core_av_base, HDMI_CORE_AV_HDMI_CTRL);
hdmi_read_reg(core->base, r))
hdmi_read_reg(hdmi_av_base(core), r))
hdmi_read_reg(hdmi_av_base(core), CORE_REG(i, r)))
r = hdmi_read_reg(av_base, HDMI_CORE_AV_ACR_CTRL);
r = hdmi_read_reg(av_base, HDMI_CORE_AV_I2S_IN_CTRL);
r = hdmi_read_reg(av_base, HDMI_CORE_AV_AUD_MODE);
v = hdmi_read_reg(hdmi->phy.base, HDMI_TXPHY_PAD_CFG_CTRL);
hdmi_read_reg(core->base, r))
r = hdmi_read_reg(base, HDMI_CORE_FC_INVIDCONF);
hdmi_read_reg(phy->base, HDMI_TXPHY_TX_CTRL);
hdmi_read_reg(phy->base, r))
hdmi_read_reg(pll->base, r))
v = hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS_RAW);
r = hdmi_read_reg(wp->base, HDMI_WP_VIDEO_CFG);
#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, hdmi_read_reg(wp->base, r))
r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG);
r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG2);
r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CTRL);
return hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS);
hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS);
hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\
FLD_GET(hdmi_read_reg(base, idx), start, end)
r = hdmi_read_reg(core_sys_base, HDMI_CORE_SYS_SYS_CTRL1);
r = hdmi_read_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE);
r = hdmi_read_reg(core_av_base, HDMI_CORE_AV_HDMI_CTRL);
hdmi_read_reg(core->base, r))
hdmi_read_reg(hdmi_av_base(core), r))
hdmi_read_reg(hdmi_av_base(core), CORE_REG(i, r)))
r = hdmi_read_reg(av_base, HDMI_CORE_AV_ACR_CTRL);
r = hdmi_read_reg(av_base, HDMI_CORE_AV_I2S_IN_CTRL);
r = hdmi_read_reg(av_base, HDMI_CORE_AV_AUD_MODE);
v = hdmi_read_reg(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL);
hdmi_read_reg(core->base, r))
r = hdmi_read_reg(base, HDMI_CORE_FC_INVIDCONF);
hdmi_read_reg(phy->base, HDMI_TXPHY_TX_CTRL);
hdmi_read_reg(phy->base, r))
hdmi_read_reg(pll->base, r))
v = hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS_RAW);
r = hdmi_read_reg(wp->base, HDMI_WP_VIDEO_CFG);
r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG);
#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, hdmi_read_reg(wp->base, r))
r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG2);
r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CTRL);
return hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS);
hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS);