drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c

39

#define hw_clk_to_pll(x) container_of(x, struct hdmi_pll_8996, clk_hw)

drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c

398

struct hdmi_pll_8996 *pll = hw_clk_to_pll(hw);

drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c

567

static int hdmi_8996_pll_lock_status(struct hdmi_pll_8996 *pll)

drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c

594

struct hdmi_pll_8996 *pll = hw_clk_to_pll(hw);

drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c

643

struct hdmi_pll_8996 *pll = hw_clk_to_pll(hw);

drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c

662

struct hdmi_pll_8996 *pll = hw_clk_to_pll(hw);

drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c

671

struct hdmi_pll_8996 *pll = hw_clk_to_pll(hw);

drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c

703

struct hdmi_pll_8996 *pll;

drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c

81

static inline struct hdmi_phy *pll_get_phy(struct hdmi_pll_8996 *pll)

drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c

86

static inline void hdmi_pll_write(struct hdmi_pll_8996 *pll, int offset,

drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c

92

static inline u32 hdmi_pll_read(struct hdmi_pll_8996 *pll, int offset)

drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c

97

static inline void hdmi_tx_chan_write(struct hdmi_pll_8996 *pll, int channel,