drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c

41

#define hw_clk_to_pll(x) container_of(x, struct hdmi_pll_8998, clk_hw)

drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c

447

struct hdmi_pll_8998 *pll = hw_clk_to_pll(hw);

drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c

589

static int hdmi_8998_pll_lock_status(struct hdmi_pll_8998 *pll)

drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c

612

struct hdmi_pll_8998 *pll = hw_clk_to_pll(hw);

drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c

660

struct hdmi_pll_8998 *pll = hw_clk_to_pll(hw);

drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c

666

struct hdmi_pll_8998 *pll = hw_clk_to_pll(hw);

drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c

675

struct hdmi_pll_8998 *pll = hw_clk_to_pll(hw);

drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c

707

struct hdmi_pll_8998 *pll;

drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c

80

static inline struct hdmi_phy *pll_get_phy(struct hdmi_pll_8998 *pll)

drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c

85

static inline void hdmi_pll_write(struct hdmi_pll_8998 *pll, int offset,

drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c

91

static inline u32 hdmi_pll_read(struct hdmi_pll_8998 *pll, int offset)

drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c

96

static inline void hdmi_tx_chan_write(struct hdmi_pll_8998 *pll, int channel,