drivers/gpu/drm/tegra/gr3d.c

106

struct gr3d *gr3d = to_gr3d(drm);

drivers/gpu/drm/tegra/gr3d.c

115

host1x_channel_put(gr3d->channel);

drivers/gpu/drm/tegra/gr3d.c

117

gr3d->channel = NULL;

drivers/gpu/drm/tegra/gr3d.c

130

struct gr3d *gr3d = to_gr3d(client);

drivers/gpu/drm/tegra/gr3d.c

132

context->channel = host1x_channel_get(gr3d->channel);

drivers/gpu/drm/tegra/gr3d.c

146

struct gr3d *gr3d = dev_get_drvdata(dev);

drivers/gpu/drm/tegra/gr3d.c

159

if (test_bit(offset, gr3d->addr_regs))

drivers/gpu/drm/tegra/gr3d.c

309

struct gr3d *gr3d = dev_get_drvdata(dev);

drivers/gpu/drm/tegra/gr3d.c

320

if (gr3d->nclocks == 1) {

drivers/gpu/drm/tegra/gr3d.c

324

clk = gr3d->clocks[0].clk;

drivers/gpu/drm/tegra/gr3d.c

326

for (i = 0; i < gr3d->nclocks; i++) {

drivers/gpu/drm/tegra/gr3d.c

327

if (WARN_ON(!gr3d->clocks[i].id))

drivers/gpu/drm/tegra/gr3d.c

330

if (!strcmp(gr3d->clocks[i].id, name)) {

drivers/gpu/drm/tegra/gr3d.c

331

clk = gr3d->clocks[i].clk;

drivers/gpu/drm/tegra/gr3d.c

336

if (WARN_ON(i == gr3d->nclocks))

drivers/gpu/drm/tegra/gr3d.c

354

err = tegra_pmc_powergate_sequence_power_up(gr3d->pmc, id,

drivers/gpu/drm/tegra/gr3d.c

372

static int gr3d_init_power(struct device *dev, struct gr3d *gr3d)

drivers/gpu/drm/tegra/gr3d.c

387

gr3d->pmc = devm_tegra_pmc_get(dev);

drivers/gpu/drm/tegra/gr3d.c

388

if (IS_ERR(gr3d->pmc))

drivers/gpu/drm/tegra/gr3d.c

389

return dev_err_probe(dev, PTR_ERR(gr3d->pmc),

drivers/gpu/drm/tegra/gr3d.c

417

err = devm_pm_domain_attach_list(dev, &pd_data, &gr3d->pd_list);

drivers/gpu/drm/tegra/gr3d.c

424

static int gr3d_get_clocks(struct device *dev, struct gr3d *gr3d)

drivers/gpu/drm/tegra/gr3d.c

428

err = devm_clk_bulk_get_all(dev, &gr3d->clocks);

drivers/gpu/drm/tegra/gr3d.c

433

gr3d->nclocks = err;

drivers/gpu/drm/tegra/gr3d.c

435

if (gr3d->nclocks != gr3d->soc->num_clocks) {

drivers/gpu/drm/tegra/gr3d.c

436

dev_err(dev, "invalid number of clocks: %u\n", gr3d->nclocks);

drivers/gpu/drm/tegra/gr3d.c

443

static int gr3d_get_resets(struct device *dev, struct gr3d *gr3d)

drivers/gpu/drm/tegra/gr3d.c

447

gr3d->resets[RST_MC].id = "mc";

drivers/gpu/drm/tegra/gr3d.c

448

gr3d->resets[RST_MC2].id = "mc2";

drivers/gpu/drm/tegra/gr3d.c

449

gr3d->resets[RST_GR3D].id = "3d";

drivers/gpu/drm/tegra/gr3d.c

450

gr3d->resets[RST_GR3D2].id = "3d2";

drivers/gpu/drm/tegra/gr3d.c

451

gr3d->nresets = gr3d->soc->num_resets;

drivers/gpu/drm/tegra/gr3d.c

454

dev, gr3d->nresets, gr3d->resets);

drivers/gpu/drm/tegra/gr3d.c

460

if (WARN_ON(!gr3d->resets[RST_GR3D].rstc) ||

drivers/gpu/drm/tegra/gr3d.c

461

WARN_ON(!gr3d->resets[RST_GR3D2].rstc && gr3d->nresets == 4))

drivers/gpu/drm/tegra/gr3d.c

470

struct gr3d *gr3d;

drivers/gpu/drm/tegra/gr3d.c

474

gr3d = devm_kzalloc(&pdev->dev, sizeof(*gr3d), GFP_KERNEL);

drivers/gpu/drm/tegra/gr3d.c

475

if (!gr3d)

drivers/gpu/drm/tegra/gr3d.c

478

platform_set_drvdata(pdev, gr3d);

drivers/gpu/drm/tegra/gr3d.c

480

gr3d->soc = of_device_get_match_data(&pdev->dev);

drivers/gpu/drm/tegra/gr3d.c

486

err = gr3d_get_clocks(&pdev->dev, gr3d);

drivers/gpu/drm/tegra/gr3d.c

490

err = gr3d_get_resets(&pdev->dev, gr3d);

drivers/gpu/drm/tegra/gr3d.c

494

err = gr3d_init_power(&pdev->dev, gr3d);

drivers/gpu/drm/tegra/gr3d.c

498

INIT_LIST_HEAD(&gr3d->client.base.list);

drivers/gpu/drm/tegra/gr3d.c

499

gr3d->client.base.ops = &gr3d_client_ops;

drivers/gpu/drm/tegra/gr3d.c

500

gr3d->client.base.dev = &pdev->dev;

drivers/gpu/drm/tegra/gr3d.c

501

gr3d->client.base.class = HOST1X_CLASS_GR3D;

drivers/gpu/drm/tegra/gr3d.c

502

gr3d->client.base.syncpts = syncpts;

drivers/gpu/drm/tegra/gr3d.c

503

gr3d->client.base.num_syncpts = 1;

drivers/gpu/drm/tegra/gr3d.c

505

INIT_LIST_HEAD(&gr3d->client.list);

drivers/gpu/drm/tegra/gr3d.c

506

gr3d->client.version = gr3d->soc->version;

drivers/gpu/drm/tegra/gr3d.c

507

gr3d->client.ops = &gr3d_ops;

drivers/gpu/drm/tegra/gr3d.c

515

set_bit(gr3d_addr_regs[i], gr3d->addr_regs);

drivers/gpu/drm/tegra/gr3d.c

519

err = host1x_client_register(&gr3d->client.base);

drivers/gpu/drm/tegra/gr3d.c

535

struct gr3d *gr3d = platform_get_drvdata(pdev);

drivers/gpu/drm/tegra/gr3d.c

538

host1x_client_unregister(&gr3d->client.base);

drivers/gpu/drm/tegra/gr3d.c

543

struct gr3d *gr3d = dev_get_drvdata(dev);

drivers/gpu/drm/tegra/gr3d.c

546

host1x_channel_stop(gr3d->channel);

drivers/gpu/drm/tegra/gr3d.c

548

err = reset_control_bulk_assert(gr3d->nresets, gr3d->resets);

drivers/gpu/drm/tegra/gr3d.c

55

static inline struct gr3d *to_gr3d(struct tegra_drm_client *client)

drivers/gpu/drm/tegra/gr3d.c

562

clk_bulk_disable_unprepare(gr3d->nclocks, gr3d->clocks);

drivers/gpu/drm/tegra/gr3d.c

563

reset_control_bulk_release(gr3d->nresets, gr3d->resets);

drivers/gpu/drm/tegra/gr3d.c

57

return container_of(client, struct gr3d, client);

drivers/gpu/drm/tegra/gr3d.c

570

struct gr3d *gr3d = dev_get_drvdata(dev);

drivers/gpu/drm/tegra/gr3d.c

573

err = reset_control_bulk_acquire(gr3d->nresets, gr3d->resets);

drivers/gpu/drm/tegra/gr3d.c

579

err = clk_bulk_prepare_enable(gr3d->nclocks, gr3d->clocks);

drivers/gpu/drm/tegra/gr3d.c

585

err = reset_control_bulk_deassert(gr3d->nresets, gr3d->resets);

drivers/gpu/drm/tegra/gr3d.c

594

clk_bulk_disable_unprepare(gr3d->nclocks, gr3d->clocks);

drivers/gpu/drm/tegra/gr3d.c

596

reset_control_bulk_release(gr3d->nresets, gr3d->resets);

drivers/gpu/drm/tegra/gr3d.c

65

struct gr3d *gr3d = to_gr3d(drm);

drivers/gpu/drm/tegra/gr3d.c

68

gr3d->channel = host1x_channel_request(client);

drivers/gpu/drm/tegra/gr3d.c

69

if (!gr3d->channel)

drivers/gpu/drm/tegra/gr3d.c

98

host1x_channel_put(gr3d->channel);