hclgevf_read_dev
reg_val = hclgevf_read_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG);
hclgevf_read_dev(&hdev->hw, HCLGEVF_MISC_VECTOR_REG_BASE));
hclgevf_read_dev(&hdev->hw, HCLGE_COMM_VECTOR0_CMDQ_STATE_REG));
hclgevf_read_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG));
hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING));
cmdq_stat_reg = hclgevf_read_dev(&hdev->hw,
rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING);
val = hclgevf_read_dev(&hdev->hw, HCLGEVF_VF_RST_ING);
return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING);
u32 tail = hclgevf_read_dev(hw, HCLGE_COMM_NIC_CRQ_TAIL_REG);
*reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]);
*reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]);
*reg++ = hclgevf_read_dev(&hdev->hw,