gpio_generic_read_reg
imask = gpio_generic_read_reg(&bank->chip,
iedge_config = gpio_generic_read_reg(&bank->chip,
iedge_insensitive = gpio_generic_read_reg(&bank->chip,
ilevel = gpio_generic_read_reg(&bank->chip,
bank->saved_regs[i] = gpio_generic_read_reg(&bank->chip,
return gpio_generic_read_reg(&bank->chip, reg_base + GIO_STAT(bank->id)) &
gpio_generic_read_reg(&bank->chip, reg_base + GIO_MASK(bank->id));
return gpio_generic_read_reg(chip, reg_base + gpio_reg_convert(gpio, offset));
ipol = gpio_generic_read_reg(&priv->chip, priv->regs + GRGPIO_IPOL) & ~mask;
iedge = gpio_generic_read_reg(&priv->chip, priv->regs + GRGPIO_IEDGE) & ~mask;
priv->imask = gpio_generic_read_reg(&priv->chip, regs + GRGPIO_IMASK);
mask = gpio_generic_read_reg(&mpc8xxx_gc->chip,
gpio_generic_read_reg(&mpc8xxx_gc->chip,
gpio_generic_read_reg(&mpc8xxx_gc->chip,
gpio_generic_read_reg(&mpc8xxx_gc->chip,
gpio_generic_read_reg(&mpc8xxx_gc->chip,
gpio_generic_read_reg(&mpc8xxx_gc->chip,
(gpio_generic_read_reg(&mpc8xxx_gc->chip,
(gpio_generic_read_reg(&mpc8xxx_gc->chip,
(gpio_generic_read_reg(&mpc8xxx_gc->chip,
gpio_generic_read_reg(&mpc8xxx_gc->chip,
gpio_generic_read_reg(&mpc8xxx_gc->chip,
out_mask = gpio_generic_read_reg(&mpc8xxx_gc->chip,
val = gpio_generic_read_reg(&mpc8xxx_gc->chip,
return gpio_generic_read_reg(&rg->chip, mtk->base + offset);
data = gpio_generic_read_reg(chip, reg);