gt_to_tile
rx_tile = gt_to_tile(rx_gt)->id;
if (gt_to_tile(test_gt)->id != tx_tile)
u32 near_tile = gt_to_tile(near_gt)->id;
u32 far_tile = gt_to_tile(far_gt)->id;
tile = gt_to_tile(remote_gt)->id;
kunit_info(test, "[%d.%d] Assigned 0x%p\n", gt_to_tile(root_gt)->id, root_gt->info.id, bo);
gt_to_tile(gt)->id, gt->info.id, gt->uc.guc.g2g.bo);
gt_to_tile(gt)->id, gt->info.id, bo);
gt_to_tile(gt)->id, gt->info.id, bo);
u32 near_tile = gt_to_tile(gt)->id;
tile = gt_to_tile(remote_gt)->id;
gt_to_tile(gt)->id, G2G_DEV(gt), far_tile, far_dev);
xe_tile_assert_msg(gt_to_tile(__gt), condition, "GT: %u type %d\n" msg, \
struct xe_tile *tile = gt_to_tile(gt);
struct xe_tile *tile = gt_to_tile(q->gt);
struct xe_tile *tile = gt_to_tile(q->gt);
struct xe_tile *tile = gt_to_tile(gt);
struct xe_tile *tile = gt_to_tile(gt);
struct xe_tile *tile = gt_to_tile(gt);
struct xe_tile *tile = gt_to_tile(gt);
struct xe_tile *tile = gt_to_tile(gt);
struct xe_tile *tile = gt_to_tile(gt);
err = xe_ggtt_init(gt_to_tile(gt)->mem.ggtt);
xe_lmtt_init(>_to_tile(gt)->sriov.pf.lmtt);
gt->usm.bb_pool = xe_sa_bo_manager_init(gt_to_tile(gt),
struct xe_tile *tile = gt_to_tile(gt);
xe_lmtt_init_hw(>_to_tile(gt)->sriov.pf.lmtt);
struct xe_tile *tile = gt_to_tile(gt);
xe_lmtt_init_hw(>_to_tile(gt)->sriov.pf.lmtt);
struct xe_tile *tile = gt_to_tile(gt);
struct xe_tile *tile = gt_to_tile(gt);
struct xe_gt *primary_gt = gt_to_tile(gt)->primary_gt;
struct xe_ggtt *ggtt = gt_to_tile(gt)->mem.ggtt;
u64 ggtt_start = xe_ggtt_start(gt_to_tile(gt)->mem.ggtt);
u64 ggtt_size = xe_ggtt_size(gt_to_tile(gt)->mem.ggtt);
pf_release_ggtt(gt_to_tile(gt), config->ggtt_region);
struct xe_tile *tile = gt_to_tile(gt);
size = pf_get_vf_config_ggtt(gt_to_tile(gt)->primary_gt, vfid);
size = pf_get_spare_ggtt(gt_to_tile(gt)->primary_gt);
struct xe_ggtt *ggtt = gt_to_tile(gt)->mem.ggtt;
u64 ggtt_size = xe_tile_sriov_vf_ggtt(gt_to_tile(gt));
u64 ggtt_base = xe_tile_sriov_vf_ggtt_base(gt_to_tile(gt));
lmem_size = xe_tile_sriov_vf_lmem(gt_to_tile(gt));
struct xe_gt *primary_gt = gt_to_tile(gt)->primary_gt;
struct xe_memirq *memirq = >_to_tile(gt)->memirq;
struct xe_memirq *memirq = >_to_tile(gt)->memirq;
struct xe_tile *tile = gt_to_tile(gt);
xe_tile_sriov_vf_fixup_ggtt_nodes_locked(gt_to_tile(gt), shift);
struct xe_tile *tile = gt_to_tile(gt);
struct xe_tile *tile = gt_to_tile(gt);
const struct xe_gt * : (const struct xe_device *)(gt_to_tile(gt__)->xe), \
struct xe_gt * : gt_to_tile(gt__)->xe)
struct xe_tile *tile = gt_to_tile(gt);
u32 near_tile = gt_to_tile(near_gt)->id;
u32 far_tile = gt_to_tile(far_gt)->id;
struct xe_tile *tile = gt_to_tile(gt);
far_tile = gt_to_tile(far_gt)->id;
tile = gt_to_tile(far_gt)->id;
addr = __xe_bo_ggtt_addr(bo, gt_to_tile(guc_to_gt(guc))->id);
struct xe_tile *tile = gt_to_tile(guc_to_gt(guc));
struct xe_tile *tile = gt_to_tile(gt);
sam = __xe_sa_bo_manager_init(gt_to_tile(gt), size, 0, sizeof(u32), 0);
struct xe_tile *tile = gt_to_tile(gt);
struct xe_tile *tile = gt_to_tile(gt);
struct xe_tile *tile = gt_to_tile(gt);
struct xe_tile *tile = gt_to_tile(gt);
struct xe_tile *tile = gt_to_tile(log_to_gt(log));
XE_WARN_ON(xe_pcode_init_min_freq_table(gt_to_tile(pc_to_gt(pc)), min, max));
struct xe_tile *tile = gt_to_tile(gt);
struct xe_tile *tile = gt_to_tile(pc_to_gt(pc));
struct xe_tile *tile = gt_to_tile(huc_to_gt(huc));
bo = xe_managed_bo_create_pin_map(xe, gt_to_tile(gt),
struct xe_tile *tile = gt_to_tile(gt);
u64 desc = xe_vm_pdp4_descriptor(vm, gt_to_tile(lrc->gt));
struct xe_tile *tile = gt_to_tile(gt);
struct xe_memirq *memirq = >_to_tile(hwe->gt)->memirq;
struct xe_migrate *m = gt_to_tile(q->gt)->migrate;
struct xe_tile *tile = gt_to_tile(gt);
struct xe_tile *tile = gt_to_tile(gt);
struct xe_tile *tile = gt_to_tile(gt);
struct xe_tile *tile = gt_to_tile(gt);
gt_list->gt_list[iter].tile_id = gt_to_tile(gt)->id;
BIT(gt_to_tile(gt)->mem.vram->id) << 1;
struct xe_tile *tile = gt_to_tile(gt);
struct xe_tile *tile = gt_to_tile(gt);
xe_assert_msg(xe, offset == (xe_mmio_read64_2x32(>_to_tile(gt)->mmio, GSMBASE) -