drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2574

struct gsl_params *gsl = &params->tg_set_gsl_params.gsl;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3493

struct gsl_params gsl)

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c

1219

const struct dcp_gsl_params *gsl_params)

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c

1235

gsl_params->gsl_master == tg->inst,

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c

1255

gsl_params->gsl_master,

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h

171

const struct dcp_gsl_params *gsl_params);

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

622

const struct dcp_gsl_params *gsl_params)

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

247

const struct dcp_gsl_params *gsl_params)

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

266

FD(DCP0_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN), gsl_params->gsl_master == tg->inst,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2723

struct dcp_gsl_params gsl_params = { 0 };

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2732

gsl_params.gsl_group = 0;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2733

gsl_params.gsl_master = grouped_pipes[0]->stream_res.tg->inst;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2737

grouped_pipes[i]->stream_res.tg, &gsl_params);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2745

gsl_params.gsl_group);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2769

struct dcp_gsl_params gsl_params = { 0 };

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2773

gsl_params.gsl_group = 0;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2774

gsl_params.gsl_master = 0;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2778

grouped_pipes[i]->stream_res.tg, &gsl_params);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2785

gsl_params.gsl_master,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

223

struct gsl_params gsl;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

226

memset(&gsl, 0, sizeof(struct gsl_params));

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3358

struct gsl_params gsl;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3361

memset(&gsl, 0, sizeof(struct gsl_params));

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1807

struct gsl_params gsl);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

291

struct gsl_params gsl;

drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h

395

const struct dcp_gsl_params *gsl_params);

drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h

489

void (*set_gsl)(struct timing_generator *optc, const struct gsl_params *params);

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

87

const struct gsl_params *params)

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h

95

const struct gsl_params *params);