drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

443

regs_and_bypass->dispclk_bypass = get_reg_field_value(internal.CLK8_CLK0_BYPASS_CNTL, CLK8_CLK0_BYPASS_CNTL, CLK0_BYPASS_SEL);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

444

regs_and_bypass->dppclk_bypass = get_reg_field_value(internal.CLK8_CLK1_BYPASS_CNTL, CLK8_CLK1_BYPASS_CNTL, CLK1_BYPASS_SEL);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

445

regs_and_bypass->dprefclk_bypass = get_reg_field_value(internal.CLK8_CLK2_BYPASS_CNTL, CLK8_CLK2_BYPASS_CNTL, CLK2_BYPASS_SEL);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

446

regs_and_bypass->dcfclk_bypass = get_reg_field_value(internal.CLK8_CLK3_BYPASS_CNTL, CLK8_CLK3_BYPASS_CNTL, CLK3_BYPASS_SEL);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

146

regs_and_bypass->dispclk_bypass = get_reg_field_value(internal.CLK5_CLK0_BYPASS_CNTL, CLK5_CLK0_BYPASS_CNTL, CLK0_BYPASS_SEL);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

147

regs_and_bypass->dppclk_bypass = get_reg_field_value(internal.CLK5_CLK1_BYPASS_CNTL, CLK5_CLK1_BYPASS_CNTL, CLK1_BYPASS_SEL);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

148

regs_and_bypass->dprefclk_bypass = get_reg_field_value(internal.CLK5_CLK2_BYPASS_CNTL, CLK5_CLK2_BYPASS_CNTL, CLK2_BYPASS_SEL);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

149

regs_and_bypass->dcfclk_bypass = get_reg_field_value(internal.CLK5_CLK3_BYPASS_CNTL, CLK5_CLK3_BYPASS_CNTL, CLK3_BYPASS_SEL);

drivers/gpu/drm/amd/display/dc/dce/dce_audio.c

1172

port_connectivity = get_reg_field_value(value,

drivers/gpu/drm/amd/display/dc/dce/dce_audio.c

728

field = get_reg_field_value(value,

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

100

uint32_t field = get_reg_field_value(

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

113

uint32_t field = get_reg_field_value(

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

121

field = get_reg_field_value(value,

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

166

field = get_reg_field_value(

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

384

*returned_bytes = (uint8_t)get_reg_field_value(value,

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c

1795

hpd_enable = get_reg_field_value(hpd_enable, DC_HPD_CONTROL, DC_HPD_EN);

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

120

if (get_reg_field_value(

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

273

if (get_reg_field_value(value, FBC_STATUS, FBC_ENABLE_STATUS)) {

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

280

if (get_reg_field_value(value, FBC_MISC, FBC_STOP_ON_HFLIP_EVENT)) {

drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

283

if (get_reg_field_value(value, FBC_CNTL, FBC_GRPH_COMP_EN)) {

drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c

480

if (get_reg_field_value(value, UNP_GRPH_UPDATE,

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

124

bool use_set_a = (get_reg_field_value(cntl_value,

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c

565

use_set_a = get_reg_field_value(

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c

72

if (get_reg_field_value(value,

drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c

75

get_reg_field_value(value,

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c

102

field = get_reg_field_value(value, CRTC_STATUS, CRTC_V_BLANK);

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c

1286

check_point = get_reg_field_value(value_crtc_vtotal,

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c

1509

if (get_reg_field_value(pol_value,

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c

1785

bool force = get_reg_field_value(value,

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c

1788

bool vert_sync = get_reg_field_value(value1,

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c

1982

if (get_reg_field_value(

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c

1986

get_reg_field_value(

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c

201

struc_en = get_reg_field_value(

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c

206

struc_stereo_sel_ovr = get_reg_field_value(

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c

2120

field = get_reg_field_value(value, CRTC_CONTROL,

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c

2273

field = get_reg_field_value(value, CRTC_CRC_CNTL, CRTC_CRC_EN);

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c

2283

*r_cr = get_reg_field_value(value, CRTC_CRC0_DATA_RG, CRC0_R_CR);

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c

2284

*g_y = get_reg_field_value(value, CRTC_CRC0_DATA_RG, CRC0_G_Y);

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c

2288

*b_cb = get_reg_field_value(value, CRTC_CRC0_DATA_B, CRC0_B_CB);

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c

2293

*r_cr = get_reg_field_value(value, CRTC_CRC1_DATA_RG, CRC1_R_CR);

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c

2294

*g_y = get_reg_field_value(value, CRTC_CRC1_DATA_RG, CRC1_G_Y);

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c

2298

*b_cb = get_reg_field_value(value, CRTC_CRC1_DATA_B, CRC1_B_CB);

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c

518

uint32_t field = get_reg_field_value(

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c

542

position->horizontal_count = get_reg_field_value(

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c

547

position->vertical_count = get_reg_field_value(

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c

554

position->nominal_vcount = get_reg_field_value(

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c

583

*v_blank_start = get_reg_field_value(value,

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c

586

*v_blank_end = get_reg_field_value(value,

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

148

field = get_reg_field_value(value, CRTCV_STATUS, CRTC_V_BLANK);

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

162

h1 = get_reg_field_value(

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

167

v1 = get_reg_field_value(

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

174

h2 = get_reg_field_value(

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

179

v2 = get_reg_field_value(

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

613

uint32_t field = get_reg_field_value(

drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c

192

get_reg_field_value(value, SCLV_MODE, SCL_MODE),

drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c

197

get_reg_field_value(value, SCLV_MODE, SCL_PSCL_EN),

drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c

308

if (get_reg_field_value(

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

301

if (get_reg_field_value(

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

448

if (get_reg_field_value(value, FBC_STATUS, FBC_ENABLE_STATUS)) {

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

455

if (get_reg_field_value(value, FBC_MISC, FBC_STOP_ON_HFLIP_EVENT)) {

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

458

if (get_reg_field_value(value, FBC_CNTL, FBC_GRPH_COMP_EN)) {

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

474

return get_reg_field_value(

drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c

629

channels = get_reg_field_value(value_control,

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

1095

field = get_reg_field_value(value, CRTC0_CRTC_CONTROL,

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

1189

field = get_reg_field_value(value, CRTC0_CRTC_CRC_CNTL, CRTC_CRC_EN);

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

1199

*r_cr = get_reg_field_value(value, CRTC0_CRTC_CRC0_DATA_RG, CRC0_R_CR);

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

1200

*g_y = get_reg_field_value(value, CRTC0_CRTC_CRC0_DATA_RG, CRC0_G_Y);

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

1204

*b_cb = get_reg_field_value(value, CRTC0_CRTC_CRC0_DATA_B, CRC0_B_CB);

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

1209

*r_cr = get_reg_field_value(value, CRTC0_CRTC_CRC1_DATA_RG, CRC1_R_CR);

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

1210

*g_y = get_reg_field_value(value, CRTC0_CRTC_CRC1_DATA_RG, CRC1_G_Y);

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

1214

*b_cb = get_reg_field_value(value, CRTC0_CRTC_CRC1_DATA_B, CRC1_B_CB);

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

177

uint32_t field = get_reg_field_value(

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

194

position->horizontal_count = get_reg_field_value(value,

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

197

position->vertical_count = get_reg_field_value(value,

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

205

position->nominal_vcount = get_reg_field_value(value,

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

256

get_reg_field_value(value_crtc_vtotal,

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

320

if (get_reg_field_value(pol_value,

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

380

return get_reg_field_value(value,

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

608

*v_blank_start = get_reg_field_value(v_blank_start_end,

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

611

*v_blank_end = get_reg_field_value(v_blank_start_end,

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

725

if (get_reg_field_value(

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

729

get_reg_field_value(

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

95

field = get_reg_field_value(value, CRTC0_CRTC_STATUS, CRTC_V_BLANK);

drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.c

188

field = get_reg_field_value(value, CRTC_CONTROL,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

165

chunk_int = get_reg_field_value(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

170

chunk_mul = get_reg_field_value(

drivers/gpu/drm/amd/display/dc/hwss/dce112/dce112_hwseq.c

79

chunk_int = get_reg_field_value(

drivers/gpu/drm/amd/display/dc/hwss/dce112/dce112_hwseq.c

84

chunk_mul = get_reg_field_value(

drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c

116

chunk_int = get_reg_field_value(

drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c

121

chunk_mul = get_reg_field_value(

drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

47

uint32_t current_status = get_reg_field_value(value,

drivers/gpu/drm/amd/display/dc/irq/irq_service.c

198

get_reg_field_value(

drivers/gpu/drm/amd/display/dc/irq/irq_service.c

225

get_reg_field_value(

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

680

straps->audio_stream_number = get_reg_field_value(reg_val,

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

683

straps->hdmi_disable = get_reg_field_value(reg_val,

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

688

straps->dc_pinstraps_audio = get_reg_field_value(reg_val,