grcan_write_reg
grcan_write_reg(®s->txctrl, txctrl);
grcan_write_reg(®s->rxctrl, GRCAN_RXCTRL_ENABLE);
grcan_write_reg(®s->ctrl, GRCAN_CTRL_ENABLE);
grcan_write_reg(®s->rxrd, rd);
grcan_write_reg(®s->txwr,
grcan_write_reg(®s->ctrl, GRCAN_CTRL_RESET);
grcan_write_reg(reg, grcan_read_reg(reg) & ~mask);
grcan_write_reg(reg, grcan_read_reg(reg) | mask);
grcan_write_reg(reg, (old & ~mask) | (value & mask));
grcan_write_reg(®s->conf, config);
grcan_write_reg(®s->rxmask, 0);
grcan_write_reg(®s->imr, GRCAN_IRQ_NONE);
grcan_write_reg(®s->txrd, txrd);
grcan_write_reg(®s->picr, sources);
grcan_write_reg(®s->txaddr, txaddr);
grcan_write_reg(®s->txsize, txsize);
grcan_write_reg(®s->txwr, txwr);
grcan_write_reg(®s->txrd, txrd);
grcan_write_reg(®s->rxaddr, rxaddr);
grcan_write_reg(®s->rxsize, rxsize);
grcan_write_reg(®s->rxwr, rxwr);
grcan_write_reg(®s->rxrd, rxrd);
grcan_write_reg(®s->imr, imr);
grcan_write_reg(®s->txctrl, GRCAN_TXCTRL_ENABLE
grcan_write_reg(®s->rxctrl, GRCAN_RXCTRL_ENABLE);
grcan_write_reg(®s->ctrl, GRCAN_CTRL_ENABLE);
grcan_write_reg(®s->txaddr, priv->dma.tx.handle);
grcan_write_reg(®s->txsize, priv->dma.tx.size);
grcan_write_reg(®s->rxaddr, priv->dma.rx.handle);
grcan_write_reg(®s->rxsize, priv->dma.rx.size);
grcan_write_reg(®s->imr, GRCAN_IRQ_DEFAULT);