grcan_read_reg
rd = grcan_read_reg(®s->rxrd);
wr = grcan_read_reg(®s->rxwr);
grcan_read_reg(®s->txrd) == txwr) {
txwr = grcan_read_reg(®s->txwr);
txctrl = grcan_read_reg(®s->txctrl);
txrd = grcan_read_reg(®s->txrd);
grcan_write_reg(reg, grcan_read_reg(reg) & ~mask);
grcan_write_reg(reg, grcan_read_reg(reg) | mask);
return grcan_read_reg(reg) & mask;
u32 old = grcan_read_reg(reg);
u32 status = grcan_read_reg(®s->stat);
u32 config = grcan_read_reg(®s->conf);
priv->eskbp = grcan_read_reg(®s->txrd);
u32 txrd = grcan_read_reg(®s->txrd);
txrd = grcan_read_reg(®s->txrd);
txrd = grcan_read_reg(®s->txrd);
u32 txwr = grcan_read_reg(®s->txwr);
sources = grcan_read_reg(®s->pimsr);
status = grcan_read_reg(®s->stat);
u32 imr = grcan_read_reg(®s->imr);
u32 txaddr = grcan_read_reg(®s->txaddr);
u32 txsize = grcan_read_reg(®s->txsize);
u32 txwr = grcan_read_reg(®s->txwr);
u32 txrd = grcan_read_reg(®s->txrd);
u32 rxaddr = grcan_read_reg(®s->rxaddr);
u32 rxsize = grcan_read_reg(®s->rxsize);
u32 rxwr = grcan_read_reg(®s->rxwr);
u32 rxrd = grcan_read_reg(®s->rxrd);
grcan_read_reg(®s->pir);