gr_read32
status = gr_read32(&dev->regs->status);
if (gr_read32(&ep->regs->epstat) & (GR_EPSTAT_B1 | GR_EPSTAT_B0))
u32 epctrl = gr_read32(&ep->regs->epctrl);
u32 epstat = gr_read32(&ep->regs->epstat);
ep_dmactrl = gr_read32(&ep->regs->dmactrl);
u32 status = gr_read32(&dev->regs->status);
if (gr_read32(&ep->regs->dmactrl) & GR_DMACTRL_AE) {
epctrl = gr_read32(&ep->regs->epctrl);
epstat = gr_read32(&ep->regs->epstat);
epctrl = gr_read32(&ep->regs->epctrl);
u32 control = gr_read32(&dev->regs->control);
u32 status = gr_read32(&dev->regs->status);
return gr_read32(&dev->regs->status) & GR_STATUS_FN_MASK;
gr_read32(&dev->regs->control) | GR_CONTROL_RW);
control = gr_read32(&dev->regs->control);
status = gr_read32(&dev->regs->status);
dmactrl = gr_read32(&ep->regs->dmactrl);
dmactrl = gr_read32(&ep->regs->dmactrl);
epctrl = gr_read32(&dev->epo[0].regs->epctrl);
epctrl = gr_read32(&dev->epi[0].regs->epctrl);
epctrl = gr_read32(&ep->regs->epctrl);
control = gr_read32(&dev->regs->control);
control = gr_read32(&dev->regs->control) & ~GR_CONTROL_UA_MASK;
halted = gr_read32(&ep->regs->epctrl) & GR_EPCTRL_EH;