arch/mips/lantiq/xway/gptu.c

104

gptu_w32(CON_CNT | CON_EDGE_ANY | CON_SYNC | CON_CLK_INT,

arch/mips/lantiq/xway/gptu.c

106

gptu_w32(1, GPTU_RLD(clk->bits));

arch/mips/lantiq/xway/gptu.c

107

gptu_w32(gptu_r32(GPTU_IRNEN) | BIT(clk->bits), GPTU_IRNEN);

arch/mips/lantiq/xway/gptu.c

108

gptu_w32(RUN_SEN | RUN_RL, GPTU_RUN(clk->bits));

arch/mips/lantiq/xway/gptu.c

114

gptu_w32(0, GPTU_RUN(clk->bits));

arch/mips/lantiq/xway/gptu.c

115

gptu_w32(0, GPTU_CON(clk->bits));

arch/mips/lantiq/xway/gptu.c

116

gptu_w32(0, GPTU_RLD(clk->bits));

arch/mips/lantiq/xway/gptu.c

117

gptu_w32(gptu_r32(GPTU_IRNEN) & ~BIT(clk->bits), GPTU_IRNEN);

arch/mips/lantiq/xway/gptu.c

77

gptu_w32(1 << timer, GPTU_IRNCR);

arch/mips/lantiq/xway/gptu.c

83

gptu_w32(0x00, GPTU_IRNEN);

arch/mips/lantiq/xway/gptu.c

84

gptu_w32(0xff, GPTU_IRNCR);

arch/mips/lantiq/xway/gptu.c

85

gptu_w32(CLC_RMC | CLC_SUSPEND, GPTU_CLC);

arch/mips/lantiq/xway/gptu.c

90

gptu_w32(0x00, GPTU_IRNEN);

arch/mips/lantiq/xway/gptu.c

91

gptu_w32(0xff, GPTU_IRNCR);

arch/mips/lantiq/xway/gptu.c

92

gptu_w32(CLC_DISABLE, GPTU_CLC);