gpio_regs
static void __iomem *gpio_regs;
gpio_regs = of_iomap(np, 0);
if (!gpio_regs)
if (gpio_regs)
iounmap(gpio_regs);
out_le32(gpio_regs+0x10, 1 << MDIO_PIN(bus));
out_le32(gpio_regs, 1 << MDIO_PIN(bus));
out_le32(gpio_regs+0x10, 1 << MDC_PIN(bus));
out_le32(gpio_regs, 1 << MDC_PIN(bus));
out_le32(gpio_regs+0x20, (1 << MDC_PIN(bus)) | (1 << MDIO_PIN(bus)));
out_le32(gpio_regs+0x30, (1 << MDIO_PIN(bus)));
return !!(in_le32(gpio_regs+0x40) & (1 << MDIO_PIN(bus)));
static struct gpio_regs gpio_grp_regs_p0 = {
static struct gpio_regs gpio_grp_regs_p1 = {
static struct gpio_regs gpio_grp_regs_p2 = {
static struct gpio_regs gpio_grp_regs_p3 = {
struct gpio_regs *gpio_grp;
struct gpio_regs context;
data = rockchip_gpio_readl_bit(bank, offset, bank->gpio_regs->port_ddr);
rockchip_gpio_writel_bit(bank, offset, data, bank->gpio_regs->port_ddr);
rockchip_gpio_writel_bit(bank, offset, value, bank->gpio_regs->port_dr);
data = readl(bank->reg_base + bank->gpio_regs->ext_port);
const struct rockchip_gpio_regs *reg = bank->gpio_regs;
pending = readl_relaxed(bank->reg_base + bank->gpio_regs->int_status);
bank->gpio_regs->ext_port);
bank->gpio_regs->int_polarity);
bank->gpio_regs->int_polarity);
bank->gpio_regs->ext_port);
bank->gpio_regs->port_ddr);
level = rockchip_gpio_readl(bank, bank->gpio_regs->int_type);
polarity = rockchip_gpio_readl(bank, bank->gpio_regs->int_polarity);
bank->gpio_regs->int_bothedge);
data = readl(bank->reg_base + bank->gpio_regs->ext_port);
bank->gpio_regs->int_bothedge);
rockchip_gpio_writel(bank, level, bank->gpio_regs->int_type);
rockchip_gpio_writel(bank, polarity, bank->gpio_regs->int_polarity);
bank->saved_masks = irq_reg_readl(gc, bank->gpio_regs->int_mask);
irq_reg_writel(gc, ~gc->wake_active, bank->gpio_regs->int_mask);
irq_reg_writel(gc, bank->saved_masks, bank->gpio_regs->int_mask);
gc->chip_types[0].regs.mask = bank->gpio_regs->int_mask;
gc->chip_types[0].regs.ack = bank->gpio_regs->port_eoi;
rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->int_mask);
rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->port_eoi);
rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->int_en);
bank->gpio_regs = &gpio_regs_v2;
bank->gpio_regs = &gpio_regs_v1;
struct gpio_regs context;
const struct rockchip_gpio_regs *gpio_regs;
unsigned int gpio_regs[] = {CS35L45_GPIO1_CTRL1, CS35L45_GPIO2_CTRL1,
regmap_update_bits(cs35l45->regmap, gpio_regs[i],
regmap_update_bits(cs35l45->regmap, gpio_regs[i],
regmap_update_bits(cs35l45->regmap, gpio_regs[i],
regmap_update_bits(cs35l45->regmap, gpio_regs[i],