gpio_bank
static void omap_gpio_mod_init(struct gpio_bank *bank)
static int omap_gpio_chip_init(struct gpio_bank *bank, struct device *pm_dev)
static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio,
static void omap_gpio_init_context(struct gpio_bank *p)
static void omap_gpio_restore_context(struct gpio_bank *bank)
static void omap_gpio_idle(struct gpio_bank *bank, bool may_lose_context)
static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset,
static void omap_gpio_unidle(struct gpio_bank *bank)
struct gpio_bank *bank;
bank = container_of(nb, struct gpio_bank, nb);
static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset,
struct gpio_bank *bank;
static inline void omap_gpio_dbck_enable(struct gpio_bank *bank)
struct gpio_bank *bank = platform_get_drvdata(pdev);
struct gpio_bank *bank = dev_get_drvdata(dev);
struct gpio_bank *bank = dev_get_drvdata(dev);
struct gpio_bank *bank = dev_get_drvdata(dev);
static inline void omap_gpio_dbck_disable(struct gpio_bank *bank)
struct gpio_bank *bank = dev_get_drvdata(dev);
static int omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset,
static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset)
static bool omap_gpio_is_off_wakeup_capable(struct gpio_bank *bank, u32 gpio_mask)
static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio,
static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio,
static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset)
static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset)
static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset)
static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset)
struct gpio_bank *bank = omap_irq_data_get_bank(d);
static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank,
static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank)
static inline void omap_set_gpio_irqenable(struct gpio_bank *bank,
struct gpio_bank *bank = omap_irq_data_get_bank(d);
struct gpio_bank *bank = gpiobank;
struct gpio_bank *bank = omap_irq_data_get_bank(d);
struct gpio_bank *bank = omap_irq_data_get_bank(d);
struct gpio_bank *bank = omap_irq_data_get_bank(data);
struct gpio_bank *bank = omap_irq_data_get_bank(data);
struct gpio_bank *bank = omap_irq_data_get_bank(d);
struct gpio_bank *bank = omap_irq_data_get_bank(d);
struct gpio_bank *bank = omap_irq_data_get_bank(d);
struct gpio_bank *bank = dev_get_drvdata(dev);
struct gpio_bank *bank = dev_get_drvdata(dev);
void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);
static inline void omap_mpuio_init(struct gpio_bank *bank)
struct gpio_bank *bank = gpiochip_get_data(chip);
struct gpio_bank *bank = gpiochip_get_data(chip);
struct gpio_bank *bank = gpiochip_get_data(chip);
struct gpio_bank *bank;
struct gpio_bank *bank = gpiochip_get_data(chip);
struct gpio_bank *bank;
static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d)
struct gpio_bank *bank = gpiochip_get_data(chip);
struct gpio_bank *bank;
struct gpio_bank *bank;
struct gpio_bank *bank = gpiochip_get_data(chip);
static void omap_gpio_show_rev(struct gpio_bank *bank)
&npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK];
&npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK];
&npcm->gpio_bank[offset / NPCM7XX_GPIO_PER_BANK];
&npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK];
&npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK];
pctrl->gpio_bank[id].base = fwnode_iomap(child, 0);
if (!pctrl->gpio_bank[id].base)
.dat = pctrl->gpio_bank[id].base + NPCM7XX_GP_N_DIN,
.set = pctrl->gpio_bank[id].base + NPCM7XX_GP_N_DOUT,
.dirin = pctrl->gpio_bank[id].base + NPCM7XX_GP_N_IEM,
ret = gpio_generic_chip_init(&pctrl->gpio_bank[id].chip, &config);
pctrl->gpio_bank[id].irq = ret;
pctrl->gpio_bank[id].irqbase = id * NPCM7XX_GPIO_PER_BANK;
pctrl->gpio_bank[id].pinctrl_id = args.args[0];
pctrl->gpio_bank[id].chip.gc.base = args.args[1];
pctrl->gpio_bank[id].chip.gc.ngpio = args.args[2];
pctrl->gpio_bank[id].chip.gc.owner = THIS_MODULE;
pctrl->gpio_bank[id].chip.gc.parent = dev;
pctrl->gpio_bank[id].chip.gc.fwnode = child;
pctrl->gpio_bank[id].chip.gc.label = devm_kasprintf(dev, GFP_KERNEL, "%pfw", child);
if (pctrl->gpio_bank[id].chip.gc.label == NULL)
pctrl->gpio_bank[id].chip.gc.dbg_show = npcmgpio_dbg_show;
pctrl->gpio_bank[id].direction_input = pctrl->gpio_bank[id].chip.gc.direction_input;
pctrl->gpio_bank[id].chip.gc.direction_input = npcmgpio_direction_input;
pctrl->gpio_bank[id].direction_output = pctrl->gpio_bank[id].chip.gc.direction_output;
pctrl->gpio_bank[id].chip.gc.direction_output = npcmgpio_direction_output;
pctrl->gpio_bank[id].request = pctrl->gpio_bank[id].chip.gc.request;
pctrl->gpio_bank[id].chip.gc.request = npcmgpio_gpio_request;
pctrl->gpio_bank[id].chip.gc.free = pinctrl_gpio_free;
girq = &pctrl->gpio_bank[id].chip.gc.irq;
girq->parents[0] = pctrl->gpio_bank[id].irq;
&pctrl->gpio_bank[id].chip.gc,
&pctrl->gpio_bank[id]);
ret = gpiochip_add_pin_range(&pctrl->gpio_bank[id].chip.gc,
pctrl->gpio_bank[id].pinctrl_id,
pctrl->gpio_bank[id].chip.gc.base,
pctrl->gpio_bank[id].chip.gc.ngpio);
gpiochip_remove(&pctrl->gpio_bank[id].chip.gc);
gpiochip_remove(&pctrl->gpio_bank[id - 1].chip.gc);
struct npcm7xx_gpio gpio_bank[NPCM7XX_GPIO_BANK_NUM];
struct npcm8xx_gpio gpio_bank[NPCM8XX_GPIO_BANK_NUM];
&npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK];
&npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK];
&npcm->gpio_bank[offset / NPCM8XX_GPIO_PER_BANK];
&npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK];
&npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK];
&npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK];
pctrl->gpio_bank[id].base = fwnode_iomap(child, 0);
if (!pctrl->gpio_bank[id].base)
.dat = pctrl->gpio_bank[id].base + NPCM8XX_GP_N_DIN,
.set = pctrl->gpio_bank[id].base + NPCM8XX_GP_N_DOUT,
.dirin = pctrl->gpio_bank[id].base + NPCM8XX_GP_N_IEM,
ret = gpio_generic_chip_init(&pctrl->gpio_bank[id].chip, &config);
pctrl->gpio_bank[id].irq = ret;
pctrl->gpio_bank[id].irq_chip = npcmgpio_irqchip;
pctrl->gpio_bank[id].irqbase = id * NPCM8XX_GPIO_PER_BANK;
pctrl->gpio_bank[id].pinctrl_id = args.args[0];
pctrl->gpio_bank[id].chip.gc.base = -1;
pctrl->gpio_bank[id].chip.gc.ngpio = args.args[2];
pctrl->gpio_bank[id].chip.gc.owner = THIS_MODULE;
pctrl->gpio_bank[id].chip.gc.parent = dev;
pctrl->gpio_bank[id].chip.gc.fwnode = child;
pctrl->gpio_bank[id].chip.gc.label = devm_kasprintf(dev, GFP_KERNEL, "%pfw", child);
if (pctrl->gpio_bank[id].chip.gc.label == NULL)
pctrl->gpio_bank[id].chip.gc.dbg_show = npcmgpio_dbg_show;
pctrl->gpio_bank[id].direction_input = pctrl->gpio_bank[id].chip.gc.direction_input;
pctrl->gpio_bank[id].chip.gc.direction_input = npcmgpio_direction_input;
pctrl->gpio_bank[id].direction_output = pctrl->gpio_bank[id].chip.gc.direction_output;
pctrl->gpio_bank[id].chip.gc.direction_output = npcmgpio_direction_output;
pctrl->gpio_bank[id].request = pctrl->gpio_bank[id].chip.gc.request;
pctrl->gpio_bank[id].chip.gc.request = npcmgpio_gpio_request;
pctrl->gpio_bank[id].chip.gc.free = pinctrl_gpio_free;
pctrl->gpio_bank[id].debounce.set_val[i] = false;
pctrl->gpio_bank[id].chip.gc.add_pin_ranges = npcmgpio_add_pin_ranges;
girq = &pctrl->gpio_bank[id].chip.gc.irq;
girq->chip = &pctrl->gpio_bank[id].irq_chip;
girq->parents[0] = pctrl->gpio_bank[id].irq;
&pctrl->gpio_bank[id].chip.gc,
&pctrl->gpio_bank[id]);
gpio = &pctrl->gpio_bank[reg];
struct wpcm450_gpio gpio_bank[WPCM450_NUM_BANKS];