gpi_write_reg
gpi_write_reg(gpii, gpii->ieob_clr_reg, BIT(0));
gpi_write_reg(gpii, chan->ch_cntxt_base_reg + CNTXT_0_CONFIG,
gpi_write_reg(gpii, chan->ch_cntxt_base_reg + CNTXT_1_R_LENGTH, ring->len);
gpi_write_reg(gpii, chan->ch_cntxt_base_reg + CNTXT_2_RING_BASE_LSB, ring->phys_addr);
gpi_write_reg(gpii, chan->ch_cntxt_base_reg + CNTXT_3_RING_BASE_MSB,
gpi_write_reg(gpii, chan->ch_cntxt_db_reg + CNTXT_5_RING_RP_MSB - CNTXT_4_RING_RP_LSB,
gpi_write_reg(gpii, gpii->regs + GPII_n_CH_k_SCRATCH_0_OFFS(id, chid),
gpi_write_reg(gpii, gpii->regs + GPII_n_CH_k_SCRATCH_1_OFFS(id, chid), 0);
gpi_write_reg(gpii, gpii->regs + GPII_n_CH_k_SCRATCH_2_OFFS(id, chid), 0);
gpi_write_reg(gpii, gpii->regs + GPII_n_CH_k_SCRATCH_3_OFFS(id, chid), 0);
gpi_write_reg(gpii, gpii->regs + GPII_n_CH_k_QOS_OFFS(id, chid), 1);
gpi_write_reg(gpii, base + CNTXT_0_CONFIG,
gpi_write_reg(gpii, base + CNTXT_1_R_LENGTH, ring->len);
gpi_write_reg(gpii, base + CNTXT_2_RING_BASE_LSB, lower_32_bits(ring->phys_addr));
gpi_write_reg(gpii, base + CNTXT_3_RING_BASE_MSB, upper_32_bits(ring->phys_addr));
gpi_write_reg(gpii, gpii->ev_cntxt_db_reg + CNTXT_5_RING_RP_MSB - CNTXT_4_RING_RP_LSB,
gpi_write_reg(gpii, base + CNTXT_8_RING_INT_MOD, 0);
gpi_write_reg(gpii, base + CNTXT_10_RING_MSI_LSB, 0);
gpi_write_reg(gpii, base + CNTXT_11_RING_MSI_MSB, 0);
gpi_write_reg(gpii, base + CNTXT_8_RING_INT_MOD, 0);
gpi_write_reg(gpii, base + CNTXT_12_RING_RP_UPDATE_LSB, 0);
gpi_write_reg(gpii, base + CNTXT_13_RING_RP_UPDATE_MSB, 0);
gpi_write_reg(gpii, addr, tmp);
gpi_write_reg(gpii, cmd_reg, cmd);
gpi_write_reg(gpii, gchan->ch_cntxt_db_reg, p_wp);
gpi_write_reg(gpii, gpii->ev_cntxt_db_reg, p_wp);
gpi_write_reg(gpii, gpii->ieob_clr_reg, BIT(0));
gpi_write_reg(gpii, gpii->regs + offset, (u32)ch_irq);
gpi_write_reg(gpii, gpii->regs + offset, irq_stts);
gpi_write_reg(gpii, gpii->regs + offset, irq_stts);
gpi_write_reg(gpii, gpii->regs + offset, 0);
gpi_write_reg(gpii, gpii->regs + offset, ev_ch_irq);