CLK
CLK(NULL, "ck_ref", &ck_ref.hw, CK_16XX | CK_1510 | CK_310 | CK_7XX),
CLK(NULL, "ck_dpll1", &ck_dpll1.hw, CK_16XX | CK_1510 | CK_310 | CK_7XX),
CLK(NULL, "ck_dpll1out", &ck_dpll1out.clk.hw, CK_16XX),
CLK(NULL, "ck_sossi", &sossi_ck.hw, CK_16XX),
CLK(NULL, "arm_ck", &arm_ck.hw, CK_16XX | CK_1510 | CK_310),
CLK(NULL, "armper_ck", &armper_ck.clk.hw, CK_16XX | CK_1510 | CK_310),
CLK("omap_gpio.0", "ick", &arm_gpio_ck.hw, CK_1510 | CK_310),
CLK(NULL, "armxor_ck", &armxor_ck.clk.hw, CK_16XX | CK_1510 | CK_310 | CK_7XX),
CLK(NULL, "armtim_ck", &armtim_ck.clk.hw, CK_16XX | CK_1510 | CK_310),
CLK("omap_wdt", "fck", &armwdt_ck.clk.hw, CK_16XX | CK_1510 | CK_310),
CLK("omap_wdt", "ick", &armper_ck.clk.hw, CK_16XX),
CLK("omap_wdt", "ick", &dummy_ck.hw, CK_1510 | CK_310),
CLK(NULL, "arminth_ck", &arminth_ck1510.hw, CK_1510 | CK_310),
CLK(NULL, "arminth_ck", &arminth_ck16xx.hw, CK_16XX),
CLK(NULL, "dsp_ck", &dsp_ck.hw, CK_16XX | CK_1510 | CK_310),
CLK(NULL, "dspmmu_ck", &dspmmu_ck.hw, CK_16XX | CK_1510 | CK_310),
CLK(NULL, "dspper_ck", &dspper_ck.hw, CK_16XX | CK_1510 | CK_310),
CLK(NULL, "dspxor_ck", &dspxor_ck.hw, CK_16XX | CK_1510 | CK_310),
CLK(NULL, "dsptim_ck", &dsptim_ck.hw, CK_16XX | CK_1510 | CK_310),
CLK(NULL, "tc_ck", &tc_ck.clk.hw, CK_16XX | CK_1510 | CK_310 | CK_7XX),
CLK(NULL, "tipb_ck", &tipb_ck.hw, CK_1510 | CK_310),
CLK(NULL, "l3_ocpi_ck", &l3_ocpi_ck.hw, CK_16XX | CK_7XX),
CLK(NULL, "tc1_ck", &tc1_ck.hw, CK_16XX),
CLK(NULL, "tc2_ck", &tc2_ck.hw, CK_16XX),
CLK(NULL, "dma_ck", &dma_ck.hw, CK_16XX | CK_1510 | CK_310),
CLK(NULL, "dma_lcdfree_ck", &dma_lcdfree_ck.hw, CK_16XX),
CLK(NULL, "api_ck", &api_ck.clk.hw, CK_16XX | CK_1510 | CK_310 | CK_7XX),
CLK(NULL, "lb_ck", &lb_ck.clk.hw, CK_1510 | CK_310),
CLK(NULL, "rhea1_ck", &rhea1_ck.hw, CK_16XX),
CLK(NULL, "rhea2_ck", &rhea2_ck.hw, CK_16XX),
CLK(NULL, "lcd_ck", &lcd_ck_16xx.hw, CK_16XX | CK_7XX),
CLK(NULL, "lcd_ck", &lcd_ck_1510.clk.hw, CK_1510 | CK_310),
CLK(NULL, "uart1_ck", &uart1_1510.hw, CK_1510 | CK_310),
CLK(NULL, "uart1_ck", &uart1_16xx.clk.hw, CK_16XX),
CLK(NULL, "uart1_ck", &uart1_7xx.hw, CK_7XX),
CLK(NULL, "uart2_ck", &uart2_ck.hw, CK_16XX | CK_1510 | CK_310),
CLK(NULL, "uart2_ck", &uart2_7xx.hw, CK_7XX),
CLK(NULL, "uart3_ck", &uart3_1510.hw, CK_1510 | CK_310),
CLK(NULL, "uart3_ck", &uart3_16xx.clk.hw, CK_16XX),
CLK(NULL, "usb_clko", &usb_clko.hw, CK_16XX | CK_1510 | CK_310),
CLK(NULL, "usb_hhc_ck", &usb_hhc_ck1510.hw, CK_1510 | CK_310),
CLK(NULL, "usb_hhc_ck", &usb_hhc_ck16xx.hw, CK_16XX),
CLK(NULL, "usb_dc_ck", &usb_dc_ck.hw, CK_16XX | CK_7XX),
CLK(NULL, "mclk", &mclk_1510.hw, CK_1510 | CK_310),
CLK(NULL, "mclk", &mclk_16xx.hw, CK_16XX),
CLK(NULL, "bclk", &bclk_1510.hw, CK_1510 | CK_310),
CLK(NULL, "bclk", &bclk_16xx.hw, CK_16XX),
CLK("mmci-omap.0", "fck", &mmc1_ck.hw, CK_16XX | CK_1510 | CK_310),
CLK("mmci-omap.0", "fck", &mmc3_ck.hw, CK_7XX),
CLK("mmci-omap.0", "ick", &armper_ck.clk.hw, CK_16XX | CK_1510 | CK_310 | CK_7XX),
CLK("mmci-omap.1", "fck", &mmc2_ck.hw, CK_16XX),
CLK("mmci-omap.1", "ick", &armper_ck.clk.hw, CK_16XX),
CLK(NULL, "mpu", &virtual_ck_mpu.hw, CK_16XX | CK_1510 | CK_310),
CLK("omap_i2c.1", "fck", &i2c_fck.hw, CK_16XX | CK_1510 | CK_310 | CK_7XX),
CLK("omap_i2c.1", "ick", &i2c_ick.hw, CK_16XX),
CLK("omap_i2c.1", "ick", &dummy_ck.hw, CK_1510 | CK_310 | CK_7XX),
CLK("omap1_spi100k.1", "fck", &dummy_ck.hw, CK_7XX),
CLK("omap1_spi100k.1", "ick", &dummy_ck.hw, CK_7XX),
CLK("omap1_spi100k.2", "fck", &dummy_ck.hw, CK_7XX),
CLK("omap1_spi100k.2", "ick", &dummy_ck.hw, CK_7XX),
CLK("omap_uwire", "fck", &armxor_ck.clk.hw, CK_16XX | CK_1510 | CK_310),
CLK("omap-mcbsp.1", "ick", &dspper_ck.hw, CK_16XX),
CLK("omap-mcbsp.1", "ick", &dummy_ck.hw, CK_1510 | CK_310),
CLK("omap-mcbsp.2", "ick", &armper_ck.clk.hw, CK_16XX),
CLK("omap-mcbsp.2", "ick", &dummy_ck.hw, CK_1510 | CK_310),
CLK("omap-mcbsp.3", "ick", &dspper_ck.hw, CK_16XX),
CLK("omap-mcbsp.3", "ick", &dummy_ck.hw, CK_1510 | CK_310),
CLK("omap-mcbsp.1", "fck", &dspxor_ck.hw, CK_16XX | CK_1510 | CK_310),
CLK("omap-mcbsp.2", "fck", &armper_ck.clk.hw, CK_16XX | CK_1510 | CK_310),
CLK("omap-mcbsp.3", "fck", &dspxor_ck.hw, CK_16XX | CK_1510 | CK_310),
DDC_GPIO_VGA_REG_LIST(CLK),
DDC_GPIO_VGA_REG_LIST(CLK),
DDC_GPIO_VGA_REG_LIST(CLK),
DDC_GPIO_VGA_REG_LIST(CLK),
DDC_GPIO_VGA_REG_LIST(CLK),
DDC_REG_LIST(CLK, id)\
DDC_VGA_REG_LIST(CLK)\
DDC_REG_LIST_DCN2(CLK, id)\
regmap_write(regmap, 0x31, val[CLK]);
regmap_write(regmap, 0x90, val[CLK]);
regmap_write(regmap, 0x32, val[CLK]);
regmap_write(regmap, 0x91, val[CLK]);
regmap_write(regmap, 0x33, val[CLK]);
regmap_write(regmap, 0x92, val[CLK]);
regmap_write(regmap, 0x34, val[CLK]);
regmap_write(regmap, 0x93, val[CLK]);
regmap_write(regmap, 0x36, val[CLK]);
regmap_write(regmap, 0x95, val[CLK]);
regmap_write(regmap, 0x35, val[CLK]);
regmap_write(regmap, 0x94, val[CLK]);
val[CLK] = DIV_ROUND_UP(range[L] * (factor << 1), t_byteck) - 2;
val[DATA] = val[CLK];
val[CLK] = DIV_ROUND_UP(AVERAGE(range[L], range[H]), t_half_byteck) - 1;
val[CLK] = DIV_ROUND_UP(range[L] * factor + (tmp & 0xffff)
val[CLK] = DIV_ROUND_UP(range[L] * factor - constant, t_half_byteck);
val[CLK] = DIV_ROUND_UP(range[L] * factor, t_byteck) - 2;
val[DATA] = val[CLK];
val[CLK] = DIV_ROUND_UP(range[L] * factor, t_byteck) - 2;
val[DATA] = val[CLK];
u8 CLK :1;
config = GEM_BF(CLK, GEM_CLK_DIV8);
config = GEM_BF(CLK, GEM_CLK_DIV16);
config = GEM_BF(CLK, GEM_CLK_DIV32);
config = GEM_BF(CLK, GEM_CLK_DIV48);
config = GEM_BF(CLK, GEM_CLK_DIV64);
config = GEM_BF(CLK, GEM_CLK_DIV96);
config = GEM_BF(CLK, GEM_CLK_DIV128);
config = GEM_BF(CLK, GEM_CLK_DIV224);
config = MACB_BF(CLK, MACB_CLK_DIV8);
config = MACB_BF(CLK, MACB_CLK_DIV16);
config = MACB_BF(CLK, MACB_CLK_DIV32);
config = MACB_BF(CLK, MACB_CLK_DIV64);
macb_writel(bp, NCFGR, MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG));
TH1520_PAD(16, AOGPIO_7, CLK, AUD, ____, GPIO, ____, ____, 0),
TH1520_PAD(19, AOGPIO_10, CLK, AUD, ____, GPIO, ____, ____, 0),
TH1520_PAD(49, CLK_OUT_0, BSEL, CLK, ____, GPIO, ____, ____, 0),
TH1520_PAD(50, CLK_OUT_1, BSEL, CLK, ____, GPIO, ____, ____, 0),
TH1520_PAD(51, CLK_OUT_2, BSEL, CLK, ____, GPIO, ____, ____, 0),
TH1520_PAD(52, CLK_OUT_3, BSEL, CLK, ____, GPIO, ____, ____, 0),
PINGROUP(clk_32k_in, CLK, RSVD2, RSVD3, RSVD4, 0x3330, N, N, N),
PINGROUP(clk_32k_in, CLK, RSVD2, RSVD3, RSVD4, 0x3330, N, N, N),
PINGROUP(clk_32k_in, CLK, RSVD1, RSVD2, RSVD3, 0x3160, N, N, N, Y, 0x940, 12, 5, 20, 5, -1, -1, -1, -1),
void viafb_set_vclock(u32 CLK, int set_iga);