goya_pb_set_block
goya_pb_set_block(hdev, mmTPC2_RTR_BASE);
goya_pb_set_block(hdev, mmTPC2_RD_REGULATOR_BASE);
goya_pb_set_block(hdev, mmTPC2_WR_REGULATOR_BASE);
goya_pb_set_block(hdev, mmTPC3_RTR_BASE);
goya_pb_set_block(hdev, mmTPC3_RD_REGULATOR_BASE);
goya_pb_set_block(hdev, mmTPC3_WR_REGULATOR_BASE);
goya_pb_set_block(hdev, mmTPC4_RTR_BASE);
goya_pb_set_block(hdev, mmTPC4_RD_REGULATOR_BASE);
goya_pb_set_block(hdev, mmTPC4_WR_REGULATOR_BASE);
goya_pb_set_block(hdev, mmTPC5_RTR_BASE);
goya_pb_set_block(hdev, mmTPC5_RD_REGULATOR_BASE);
goya_pb_set_block(hdev, mmTPC5_WR_REGULATOR_BASE);
goya_pb_set_block(hdev, mmTPC6_RTR_BASE);
goya_pb_set_block(hdev, mmTPC6_RD_REGULATOR_BASE);
goya_pb_set_block(hdev, mmTPC6_WR_REGULATOR_BASE);
goya_pb_set_block(hdev, mmTPC7_NRTR_BASE);
goya_pb_set_block(hdev, mmTPC7_RD_REGULATOR_BASE);
goya_pb_set_block(hdev, mmTPC7_WR_REGULATOR_BASE);
goya_pb_set_block(hdev, mmPCI_NRTR_BASE);
goya_pb_set_block(hdev, mmPCI_RD_REGULATOR_BASE);
goya_pb_set_block(hdev, mmPCI_WR_REGULATOR_BASE);
goya_pb_set_block(hdev, mmSRAM_Y0_X0_BANK_BASE);
goya_pb_set_block(hdev, mmSRAM_Y0_X0_RTR_BASE);
goya_pb_set_block(hdev, mmSRAM_Y0_X1_BANK_BASE);
goya_pb_set_block(hdev, mmSRAM_Y0_X1_RTR_BASE);
goya_pb_set_block(hdev, mmSRAM_Y0_X2_BANK_BASE);
goya_pb_set_block(hdev, mmSRAM_Y0_X2_RTR_BASE);
goya_pb_set_block(hdev, mmSRAM_Y0_X3_BANK_BASE);
goya_pb_set_block(hdev, mmSRAM_Y0_X3_RTR_BASE);
goya_pb_set_block(hdev, mmSRAM_Y0_X4_BANK_BASE);
goya_pb_set_block(hdev, mmSRAM_Y0_X4_RTR_BASE);
goya_pb_set_block(hdev, mmSRAM_Y1_X0_BANK_BASE);
goya_pb_set_block(hdev, mmSRAM_Y1_X0_RTR_BASE);
goya_pb_set_block(hdev, mmSRAM_Y1_X1_BANK_BASE);
goya_pb_set_block(hdev, mmSRAM_Y1_X1_RTR_BASE);
goya_pb_set_block(hdev, mmSRAM_Y1_X2_BANK_BASE);
goya_pb_set_block(hdev, mmSRAM_Y1_X2_RTR_BASE);
goya_pb_set_block(hdev, mmSRAM_Y1_X3_BANK_BASE);
goya_pb_set_block(hdev, mmSRAM_Y1_X3_RTR_BASE);
goya_pb_set_block(hdev, mmSRAM_Y1_X4_BANK_BASE);
goya_pb_set_block(hdev, mmSRAM_Y1_X4_RTR_BASE);
goya_pb_set_block(hdev, mmSRAM_Y2_X0_BANK_BASE);
goya_pb_set_block(hdev, mmSRAM_Y2_X0_RTR_BASE);
goya_pb_set_block(hdev, mmSRAM_Y2_X1_BANK_BASE);
goya_pb_set_block(hdev, mmSRAM_Y2_X1_RTR_BASE);
goya_pb_set_block(hdev, mmSRAM_Y2_X2_BANK_BASE);
goya_pb_set_block(hdev, mmSRAM_Y2_X2_RTR_BASE);
goya_pb_set_block(hdev, mmSRAM_Y2_X3_BANK_BASE);
goya_pb_set_block(hdev, mmSRAM_Y2_X3_RTR_BASE);
goya_pb_set_block(hdev, mmSRAM_Y2_X4_BANK_BASE);
goya_pb_set_block(hdev, mmSRAM_Y2_X4_RTR_BASE);
goya_pb_set_block(hdev, mmSRAM_Y3_X0_BANK_BASE);
goya_pb_set_block(hdev, mmSRAM_Y3_X0_RTR_BASE);
goya_pb_set_block(hdev, mmSRAM_Y3_X1_BANK_BASE);
goya_pb_set_block(hdev, mmSRAM_Y3_X1_RTR_BASE);
goya_pb_set_block(hdev, mmSRAM_Y3_X2_BANK_BASE);
goya_pb_set_block(hdev, mmSRAM_Y3_X2_RTR_BASE);
goya_pb_set_block(hdev, mmSRAM_Y3_X3_BANK_BASE);
goya_pb_set_block(hdev, mmSRAM_Y3_X3_RTR_BASE);
goya_pb_set_block(hdev, mmSRAM_Y3_X4_BANK_BASE);
goya_pb_set_block(hdev, mmSRAM_Y3_X4_RTR_BASE);
goya_pb_set_block(hdev, mmSRAM_Y4_X0_BANK_BASE);
goya_pb_set_block(hdev, mmSRAM_Y4_X0_RTR_BASE);
goya_pb_set_block(hdev, mmSRAM_Y4_X1_BANK_BASE);
goya_pb_set_block(hdev, mmSRAM_Y4_X1_RTR_BASE);
goya_pb_set_block(hdev, mmSRAM_Y4_X2_BANK_BASE);
goya_pb_set_block(hdev, mmSRAM_Y4_X2_RTR_BASE);
goya_pb_set_block(hdev, mmSRAM_Y4_X3_BANK_BASE);
goya_pb_set_block(hdev, mmSRAM_Y4_X3_RTR_BASE);
goya_pb_set_block(hdev, mmSRAM_Y4_X4_BANK_BASE);
goya_pb_set_block(hdev, mmSRAM_Y4_X4_RTR_BASE);
goya_pb_set_block(hdev, mmSRAM_Y5_X0_BANK_BASE);
goya_pb_set_block(hdev, mmSRAM_Y5_X0_RTR_BASE);
goya_pb_set_block(hdev, mmSRAM_Y5_X1_BANK_BASE);
goya_pb_set_block(hdev, mmSRAM_Y5_X1_RTR_BASE);
goya_pb_set_block(hdev, mmSRAM_Y5_X2_BANK_BASE);
goya_pb_set_block(hdev, mmSRAM_Y5_X2_RTR_BASE);
goya_pb_set_block(hdev, mmSRAM_Y5_X3_BANK_BASE);
goya_pb_set_block(hdev, mmSRAM_Y5_X3_RTR_BASE);
goya_pb_set_block(hdev, mmSRAM_Y5_X4_BANK_BASE);
goya_pb_set_block(hdev, mmSRAM_Y5_X4_RTR_BASE);
goya_pb_set_block(hdev, mmPCIE_WRAP_BASE);
goya_pb_set_block(hdev, mmPCIE_CORE_BASE);
goya_pb_set_block(hdev, mmPCIE_DB_CFG_BASE);
goya_pb_set_block(hdev, mmPCIE_DB_CMD_BASE);
goya_pb_set_block(hdev, mmPCIE_AUX_BASE);
goya_pb_set_block(hdev, mmPCIE_DB_RSV_BASE);
goya_pb_set_block(hdev, mmPCIE_PHY_BASE);
goya_pb_set_block(hdev, mmTPC0_NRTR_BASE);
goya_pb_set_block(hdev, mmTPC_PLL_BASE);
goya_pb_set_block(hdev, mmDMA_NRTR_BASE);
goya_pb_set_block(hdev, mmDMA_RD_REGULATOR_BASE);
goya_pb_set_block(hdev, mmDMA_WR_REGULATOR_BASE);
goya_pb_set_block(hdev, mmDMA_CH_0_BASE);
goya_pb_set_block(hdev, mmACC_MS_ECC_MEM_0_BASE);
goya_pb_set_block(hdev, mmACC_MS_ECC_MEM_1_BASE);
goya_pb_set_block(hdev, mmACC_MS_ECC_MEM_2_BASE);
goya_pb_set_block(hdev, mmACC_MS_ECC_MEM_3_BASE);
goya_pb_set_block(hdev, mmSBA_ECC_MEM_BASE);
goya_pb_set_block(hdev, mmSBB_ECC_MEM_BASE);
goya_pb_set_block(hdev, mmDMA_CH_1_BASE);
goya_pb_set_block(hdev, mmMME1_RTR_BASE);
goya_pb_set_block(hdev, mmMME1_RD_REGULATOR_BASE);
goya_pb_set_block(hdev, mmMME1_WR_REGULATOR_BASE);
goya_pb_set_block(hdev, mmMME2_RTR_BASE);
goya_pb_set_block(hdev, mmMME2_RD_REGULATOR_BASE);
goya_pb_set_block(hdev, mmMME2_WR_REGULATOR_BASE);
goya_pb_set_block(hdev, mmMME3_RTR_BASE);
goya_pb_set_block(hdev, mmDMA_CH_2_BASE);
goya_pb_set_block(hdev, mmMME3_RD_REGULATOR_BASE);
goya_pb_set_block(hdev, mmMME3_WR_REGULATOR_BASE);
goya_pb_set_block(hdev, mmMME4_RTR_BASE);
goya_pb_set_block(hdev, mmMME4_RD_REGULATOR_BASE);
goya_pb_set_block(hdev, mmMME4_WR_REGULATOR_BASE);
goya_pb_set_block(hdev, mmMME5_RTR_BASE);
goya_pb_set_block(hdev, mmDMA_CH_3_BASE);
goya_pb_set_block(hdev, mmMME5_RD_REGULATOR_BASE);
goya_pb_set_block(hdev, mmMME5_WR_REGULATOR_BASE);
goya_pb_set_block(hdev, mmMME6_RTR_BASE);
goya_pb_set_block(hdev, mmMME6_RD_REGULATOR_BASE);
goya_pb_set_block(hdev, mmMME6_WR_REGULATOR_BASE);
goya_pb_set_block(hdev, mmDMA_CH_4_BASE);
goya_pb_set_block(hdev, mmTPC0_RD_REGULATOR_BASE);
goya_pb_set_block(hdev, mmTPC0_WR_REGULATOR_BASE);
goya_pb_set_block(hdev, mmTPC1_RTR_BASE);
goya_pb_set_block(hdev, mmTPC1_RD_REGULATOR_BASE);
goya_pb_set_block(hdev, mmTPC1_WR_REGULATOR_BASE);