drivers/gpu/drm/msm/adreno/a6xx_gmu.c

1307

ret = gmu_poll_timeout(gmu,

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

287

ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, val,

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

305

ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_HFI_CTRL_STATUS, val,

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

394

ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO, val,

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

460

ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, val,

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

485

ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, val,

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

582

ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_RSCC_CONTROL_ACK, val,

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

68

if (!gmu_poll_timeout(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS, status,

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

76

if (!gmu_poll_timeout(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS, status,

drivers/gpu/drm/msm/adreno/a6xx_hfi.c

113

ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO, val,