gmu_read
val = gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS);
status = gmu_read(gmu, REG_A6XX_GMU_GENERAL_7) == 1 ?
reg = gmu_read(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS);
gmu_read(gmu,
gmu_read(gmu,
ret = gmu_read(gmu, REG_A6XX_GMU_DCVS_RETURN);
val = gmu_read(gmu, REG_A8XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE);
val = gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE);
val = gmu_read(gmu, REG_A6XX_GMU_CM3_DTCM_START + 0xff8);
gmu_read(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO));
status = gmu_read(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_STATUS);
gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS));
gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS));
if (gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE)
gmu_read(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS));
status = gmu_read(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO);
val = gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS);
ver = gmu_read(gmu, REG_A6XX_GMU_CORE_FW_VERSION);
u32 val = gmu_read(gmu, reg);
val = gmu_read(gmu, lo);
val |= ((u64) gmu_read(gmu, hi) << 32);
u32 rbbm_unmasked = gmu_read(gmu, REG_A6XX_GMU_RBBM_INT_UNMASKED_STATUS);
count_hi = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_H);
count_lo = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L);
temp = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_H);
val = gmu_read(gmu, offset);