CLEAR
P4_ESCR_EMASK_BIT(P4_EVENT_MACHINE_CLEAR, CLEAR) |
dma_writel(dw, CLEAR.XFER, dw->all_chan_mask);
dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask);
dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask);
dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask);
dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask);
dma_writel(dw, CLEAR.XFER, dwc->mask);
dma_writel(dw, CLEAR.ERROR, dwc->mask);
struct dw_dma_irq_regs CLEAR; /* w (ack, affects "raw") */
dma_writel(idma64, CLEAR(ERROR), idma64c->mask);
dma_writel(idma64, CLEAR(XFER), idma64c->mask);
cp_wait(ctx, UNK57, CLEAR);
cp_bra (ctx, UNK54, CLEAR, cp_prepare_exit);
cp_set (ctx, UNK1D, CLEAR);
cp_set (ctx, UNK01, CLEAR);
cp_set (ctx, UNK03, CLEAR);
cp_set (ctx, UNK1D, CLEAR);
ADJD_S311_CHANNEL(CLEAR, 3),
.address = APDS9960_REG_ALS_CHANNEL(CLEAR),
BH1745_CHANNEL(CLEAR, 3, BH1745_CLEAR_LSB),
CM3323_COLOR_CHANNEL(CLEAR, CM3323_CMD_CLEAR_DATA),
CM36651_LIGHT_CHANNEL(CLEAR, CM36651_LIGHT_CHANNEL_IDX_CLEAR),
OPT4060_COLOR_CHANNEL(CLEAR, BIT(IIO_CHAN_INFO_RAW)),
OPT4060_COLOR_CHANNEL_NO_EVENTS(CLEAR, BIT(IIO_CHAN_INFO_RAW)),
TCS3414_CHANNEL(CLEAR, 3, TCS3414_DATA_CLEAR),
TCS3472_CHANNEL(CLEAR, 0, TCS3472_CDATA),
CLEAR(PLC(np,PL_INTR_MASK),PL_LE_CTR) ;
CLEAR(PLC(PA,PL_CNTRL_B),PL_CONFIG_CNTRL) ;
CLEAR(PLC(PA,PL_CNTRL_A),PL_SC_REM_LOOP) ;
CLEAR(PLC(PB,PL_CNTRL_B),PL_CONFIG_CNTRL) ;
CLEAR(PLC(PB,PL_CNTRL_A),PL_SC_REM_LOOP) ;
CLEAR(PLC(np,PL_CNTRL_B),PL_LONG) ;
CLEAR(PLC(np,PL_CNTRL_B),PL_PC_JOIN) ;
CLEAR(PLC(np,PL_CNTRL_B),PL_LONG) ;
CLEAR(PLC(np,PL_CNTRL_B),PL_PC_JOIN) ;
CLEAR(PLC(np,PL_CNTRL_B),PL_LONG) ;
CLEAR(PLC(np,PL_CNTRL_B),PL_PC_JOIN) ;
CLEAR(PLC(np,PL_CNTRL_B),PL_LONG) ;
CLEAR(PLC(np,PL_INTR_MASK),PL_LE_CTR) ; /* disable LEM int. */
if (oldcode != CLEAR && max_ent < db->maxmaxcode)
OUTPUT (CLEAR);
oldcode = CLEAR;
if (incode == CLEAR)
|| (incode > max_ent && oldcode == CLEAR))
printf(CLEAR HIDE_CURSOR