Symbol: CLASS2_ENABLE_MAILBOX_INTR
arch/powerpc/platforms/cell/spufs/backing_ops.c
132
ctx->csa.priv1.int_mask_class2_RW |= CLASS2_ENABLE_MAILBOX_INTR;
arch/powerpc/platforms/cell/spufs/backing_ops.c
98
CLASS2_ENABLE_MAILBOX_INTR;
arch/powerpc/platforms/cell/spufs/hw_ops.c
65
spu_int_mask_or(spu, 2, CLASS2_ENABLE_MAILBOX_INTR);
arch/powerpc/platforms/cell/spufs/hw_ops.c
96
spu_int_mask_or(spu, 2, CLASS2_ENABLE_MAILBOX_INTR);
arch/powerpc/platforms/cell/spufs/switch.c
1682
spu_int_stat_clear(spu, 2, CLASS2_ENABLE_MAILBOX_INTR);