gfx_info
klinfo_t gfx_info;
union gfx_info *gfx_info = (union gfx_info *)
adev->gfx.config.max_shader_engines = gfx_info->info.max_shader_engines;
adev->gfx.config.max_tile_pipes = gfx_info->info.max_tile_pipes;
adev->gfx.config.max_cu_per_sh = gfx_info->info.max_cu_per_sh;
adev->gfx.config.max_sh_per_se = gfx_info->info.max_sh_per_se;
adev->gfx.config.max_backends_per_se = gfx_info->info.max_backends_per_se;
gfx_info->info.max_texture_channel_caches;
gfx_info);
union gfx_info *gfx_info = (union gfx_info *)
spll->reference_freq = le32_to_cpu(gfx_info->v30.golden_tsc_count_lower_refclk);
spll->reference_freq = le32_to_cpu(gfx_info->v22.rlc_gpu_timer_refclk);
gfx_info);
union gfx_info *gfx_info = (union gfx_info *)
adev->gfx.config.max_shader_engines = gfx_info->v24.max_shader_engines;
adev->gfx.config.max_cu_per_sh = gfx_info->v24.max_cu_per_sh;
adev->gfx.config.max_sh_per_se = gfx_info->v24.max_sh_per_se;
adev->gfx.config.max_backends_per_se = gfx_info->v24.max_backends_per_se;
adev->gfx.config.max_texture_channel_caches = gfx_info->v24.max_texture_channel_caches;
adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v24.gc_num_gprs);
adev->gfx.config.max_gs_threads = gfx_info->v24.gc_num_max_gs_thds;
adev->gfx.config.gs_vgt_table_depth = gfx_info->v24.gc_gs_table_depth;
le16_to_cpu(gfx_info->v24.gc_gsprim_buff_depth);
gfx_info->v24.gc_double_offchip_lds_buffer;
adev->gfx.cu_info.wave_front_size = le16_to_cpu(gfx_info->v24.gc_wave_size);
adev->gfx.cu_info.max_waves_per_simd = le16_to_cpu(gfx_info->v24.gc_max_waves_per_simd);
adev->gfx.cu_info.max_scratch_slots_per_cu = gfx_info->v24.gc_max_scratch_slots_per_cu;
adev->gfx.cu_info.lds_size = le16_to_cpu(gfx_info->v24.gc_lds_size);
adev->gfx.config.max_shader_engines = gfx_info->v27.max_shader_engines;
adev->gfx.config.max_cu_per_sh = gfx_info->v27.max_cu_per_sh;
adev->gfx.config.max_sh_per_se = gfx_info->v27.max_sh_per_se;
adev->gfx.config.max_backends_per_se = gfx_info->v27.max_backends_per_se;
adev->gfx.config.max_texture_channel_caches = gfx_info->v27.max_texture_channel_caches;
adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v27.gc_num_gprs);
adev->gfx.config.max_gs_threads = gfx_info->v27.gc_num_max_gs_thds;
adev->gfx.config.gs_vgt_table_depth = gfx_info->v27.gc_gs_table_depth;
adev->gfx.config.gs_prim_buffer_depth = le16_to_cpu(gfx_info->v27.gc_gsprim_buff_depth);
adev->gfx.config.double_offchip_lds_buf = gfx_info->v27.gc_double_offchip_lds_buffer;
adev->gfx.cu_info.wave_front_size = le16_to_cpu(gfx_info->v27.gc_wave_size);
adev->gfx.cu_info.max_waves_per_simd = le16_to_cpu(gfx_info->v27.gc_max_waves_per_simd);
adev->gfx.cu_info.max_scratch_slots_per_cu = gfx_info->v27.gc_max_scratch_slots_per_cu;
adev->gfx.cu_info.lds_size = le16_to_cpu(gfx_info->v27.gc_lds_size);
adev->gfx.config.max_shader_engines = gfx_info->v30.max_shader_engines;
adev->gfx.config.max_cu_per_sh = gfx_info->v30.max_cu_per_sh;
adev->gfx.config.max_sh_per_se = gfx_info->v30.max_sh_per_se;
adev->gfx.config.max_backends_per_se = gfx_info->v30.max_backends_per_se;
adev->gfx.config.max_texture_channel_caches = gfx_info->v30.max_texture_channel_caches;
struct amdgpu_gfx_config *gfx_info = &kdev->adev->gfx.config;
cu->array_count = gfx_info->max_sh_per_se *
gfx_info->max_shader_engines;
total_num_of_cu = (cu->array_count * gfx_info->max_cu_per_sh);
cu->num_cu_per_array = gfx_info->max_cu_per_sh;
cu->num_banks = gfx_info->max_shader_engines;
struct amdgpu_gfx_config *gfx_info = &mm->dev->adev->gfx.config;
if (gfx_info->max_shader_engines > KFD_MAX_NUM_SE) {
gfx_info->max_shader_engines);
if (gfx_info->max_sh_per_se > KFD_MAX_NUM_SH_PER_SE) {
gfx_info->max_sh_per_se * gfx_info->max_shader_engines);
for (se = 0; se < gfx_info->max_shader_engines; se++)
for (sh = 0; sh < gfx_info->max_sh_per_se; sh++)
for (i = 0; i < gfx_info->max_shader_engines; i++)
for (sh = 0; sh < gfx_info->max_sh_per_se; sh++) {
for (se = 0; se < gfx_info->max_shader_engines; se++) {
struct amdgpu_gfx_config *gfx_info = &mm->dev->adev->gfx.config;
for (se = 0; se < gfx_info->max_shader_engines; se++)
for (sh = 0; sh < gfx_info->max_sh_per_se; sh++)
for (i = 0; i < gfx_info->max_shader_engines; i++)
for (sh = 0; sh < gfx_info->max_sh_per_se; sh++) {
for (se = 0; se < gfx_info->max_shader_engines; se++) {
struct amdgpu_gfx_config *gfx_info,
for (i = 0; i < gfx_info->max_shader_engines && !found; i++) {
for (j = 0; j < gfx_info->max_sh_per_se && !found; j++) {
for (i = 0; i < gfx_info->max_shader_engines; i++) {
for (j = 0; j < gfx_info->max_sh_per_se; j++) {
struct amdgpu_gfx_config *gfx_info = &kdev->adev->gfx.config;
for (i = 0; i < gfx_info->max_shader_engines; i++) {
for (j = 0; j < gfx_info->max_sh_per_se; j++) {
for (k = 0; k < gfx_info->max_cu_per_sh; k += pcache_info[ct].num_cu_shared) {
gfx_info->max_cu_per_sh) ?
(gfx_info->max_cu_per_sh - k);
cu_info, gfx_info, ct, cu_processor_id, kdev);
struct amdgpu_gfx_config *gfx_info = &gpu->adev->gfx.config;
gfx_info->max_sh_per_se;
uint16_t gfx_info;
p->gfx_rc6_ms = gfx_info[GFX_rc6].val_ull;
p->gfx_mhz = gfx_info[GFX_MHz].val;
p->gfx_act_mhz = gfx_info[GFX_ACTMHz].val;
p->sam_mc6_ms = gfx_info[SAM_mc6].val_ull;
p->sam_mhz = gfx_info[SAM_MHz].val;
p->sam_act_mhz = gfx_info[SAM_ACTMHz].val;
static struct gfx_sysfs_info gfx_info[GFX_MAX];
rewind(gfx_info[idx].fp);
fflush(gfx_info[idx].fp);
retval = fscanf(gfx_info[idx].fp, "%lld", &gfx_info[idx].val_ull);
retval = fscanf(gfx_info[idx].fp, "%d", &gfx_info[idx].val);
gfx_info[idx].fp = fopen_or_die(path, "r");
if (!gfx_info[GFX_MHz].fp)
if (!gfx_info[GFX_ACTMHz].fp)
if (gfx_info[GFX_rc6].fp)
if (gfx_info[GFX_MHz].fp)
if (gfx_info[GFX_ACTMHz].fp)
if (gfx_info[SAM_mc6].fp)
if (gfx_info[SAM_MHz].fp)
if (gfx_info[SAM_ACTMHz].fp)