get_wptr
.get_wptr = amdgpu_cper_ring_get_wptr,
u32 (*get_wptr)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
#define amdgpu_ih_get_wptr(adev, ih) (adev)->irq.ih_funcs->get_wptr((adev), (ih))
u64 (*get_wptr)(struct amdgpu_ring *ring);
#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
.get_wptr = umsch_mm_ring_get_wptr,
.get_wptr = vpe_ring_get_wptr,
.get_wptr = cik_ih_get_wptr,
.get_wptr = cik_sdma_ring_get_wptr,
.get_wptr = cz_ih_get_wptr,
.get_wptr = gfx_v10_0_ring_get_wptr_gfx,
.get_wptr = gfx_v10_0_ring_get_wptr_compute,
.get_wptr = gfx_v10_0_ring_get_wptr_compute,
.get_wptr = gfx_v11_0_ring_get_wptr_gfx,
.get_wptr = gfx_v11_0_ring_get_wptr_compute,
.get_wptr = gfx_v11_0_ring_get_wptr_compute,
.get_wptr = gfx_v12_0_ring_get_wptr_gfx,
.get_wptr = gfx_v12_0_ring_get_wptr_compute,
.get_wptr = gfx_v12_0_ring_get_wptr_compute,
.get_wptr = gfx_v12_1_ring_get_wptr_compute,
.get_wptr = gfx_v12_1_ring_get_wptr_compute,
.get_wptr = gfx_v6_0_ring_get_wptr,
.get_wptr = gfx_v6_0_ring_get_wptr,
.get_wptr = gfx_v7_0_ring_get_wptr_gfx,
.get_wptr = gfx_v7_0_ring_get_wptr_compute,
.get_wptr = gfx_v8_0_ring_get_wptr_gfx,
.get_wptr = gfx_v8_0_ring_get_wptr_compute,
.get_wptr = gfx_v8_0_ring_get_wptr_compute,
.get_wptr = gfx_v9_0_ring_get_wptr_gfx,
.get_wptr = amdgpu_sw_ring_get_wptr_gfx,
.get_wptr = gfx_v9_0_ring_get_wptr_compute,
.get_wptr = gfx_v9_0_ring_get_wptr_compute,
.get_wptr = gfx_v9_4_3_ring_get_wptr_compute,
.get_wptr = gfx_v9_4_3_ring_get_wptr_compute,
.get_wptr = iceland_ih_get_wptr,
.get_wptr = ih_v6_0_get_wptr,
.get_wptr = ih_v6_1_get_wptr,
.get_wptr = ih_v7_0_get_wptr,
.get_wptr = jpeg_v1_0_decode_ring_get_wptr,
.get_wptr = jpeg_v2_0_dec_ring_get_wptr,
.get_wptr = jpeg_v2_5_dec_ring_get_wptr,
.get_wptr = jpeg_v2_5_dec_ring_get_wptr,
.get_wptr = jpeg_v3_0_dec_ring_get_wptr,
.get_wptr = jpeg_v4_0_dec_ring_get_wptr,
.get_wptr = jpeg_v4_0_3_dec_ring_get_wptr,
.get_wptr = jpeg_v4_0_5_dec_ring_get_wptr,
.get_wptr = jpeg_v5_0_0_dec_ring_get_wptr,
.get_wptr = jpeg_v5_0_1_dec_ring_get_wptr,
.get_wptr = jpeg_v5_3_0_dec_ring_get_wptr,
.get_wptr = mes_v11_0_ring_get_wptr,
.get_wptr = mes_v12_0_ring_get_wptr,
.get_wptr = mes_v12_1_ring_get_wptr,
.get_wptr = navi10_ih_get_wptr,
.get_wptr = sdma_v2_4_ring_get_wptr,
.get_wptr = sdma_v3_0_ring_get_wptr,
.get_wptr = sdma_v4_0_ring_get_wptr,
.get_wptr = sdma_v4_0_page_ring_get_wptr,
.get_wptr = sdma_v4_4_2_ring_get_wptr,
.get_wptr = sdma_v4_4_2_page_ring_get_wptr,
.get_wptr = sdma_v5_0_ring_get_wptr,
.get_wptr = sdma_v5_2_ring_get_wptr,
.get_wptr = sdma_v6_0_ring_get_wptr,
.get_wptr = sdma_v7_0_ring_get_wptr,
.get_wptr = sdma_v7_1_ring_get_wptr,
.get_wptr = si_dma_ring_get_wptr,
.get_wptr = si_ih_get_wptr,
.get_wptr = tonga_ih_get_wptr,
.get_wptr = uvd_v3_1_ring_get_wptr,
.get_wptr = uvd_v4_2_ring_get_wptr,
.get_wptr = uvd_v5_0_ring_get_wptr,
.get_wptr = uvd_v6_0_ring_get_wptr,
.get_wptr = uvd_v6_0_ring_get_wptr,
.get_wptr = uvd_v6_0_enc_ring_get_wptr,
.get_wptr = uvd_v7_0_ring_get_wptr,
.get_wptr = uvd_v7_0_enc_ring_get_wptr,
.get_wptr = vce_v1_0_ring_get_wptr,
.get_wptr = vce_v2_0_ring_get_wptr,
.get_wptr = vce_v3_0_ring_get_wptr,
.get_wptr = vce_v3_0_ring_get_wptr,
.get_wptr = vce_v4_0_ring_get_wptr,
.get_wptr = vcn_v1_0_dec_ring_get_wptr,
.get_wptr = vcn_v1_0_enc_ring_get_wptr,
.get_wptr = vcn_v2_0_dec_ring_get_wptr,
.get_wptr = vcn_v2_0_enc_ring_get_wptr,
.get_wptr = vcn_v2_5_dec_ring_get_wptr,
.get_wptr = vcn_v2_5_enc_ring_get_wptr,
.get_wptr = vcn_v3_0_dec_ring_get_wptr,
.get_wptr = vcn_v3_0_dec_ring_get_wptr,
.get_wptr = vcn_v3_0_enc_ring_get_wptr,
.get_wptr = vcn_v4_0_unified_ring_get_wptr,
.get_wptr = vcn_v4_0_3_unified_ring_get_wptr,
.get_wptr = vcn_v4_0_5_unified_ring_get_wptr,
.get_wptr = vcn_v5_0_0_unified_ring_get_wptr,
.get_wptr = vcn_v5_0_1_unified_ring_get_wptr,
.get_wptr = vega10_ih_get_wptr,
.get_wptr = vega20_ih_get_wptr,
wptr = get_wptr(ring);
a5xx_gpu->preempt[ring->id]->wptr = get_wptr(ring);
wptr = get_wptr(ring);
empty = (get_wptr(ring) == gpu->funcs->get_rptr(gpu, ring));
wptr = get_wptr(ring);
record_ptr->wptr = get_wptr(ring);
wptr = get_wptr(ring);
empty = (get_wptr(ring) == gpu->funcs->get_rptr(gpu, ring));
wptr = get_wptr(ring);
printk("rb wptr: %d\n", get_wptr(ring));
wptr = get_wptr(ring);
uint32_t wptr = get_wptr(ring);
state->ring[i].wptr = get_wptr(gpu->rb[i]);
u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
.get_wptr = &uvd_v1_0_get_wptr,
.get_wptr = &uvd_v1_0_get_wptr,
.get_wptr = &r600_gfx_get_wptr,
.get_wptr = &r600_dma_get_wptr,
.get_wptr = &cayman_gfx_get_wptr,
.get_wptr = &cayman_dma_get_wptr,
.get_wptr = &uvd_v1_0_get_wptr,
.get_wptr = &vce_v1_0_get_wptr,
.get_wptr = &cayman_gfx_get_wptr,
.get_wptr = &cayman_dma_get_wptr,
.get_wptr = &r100_gfx_get_wptr,
.get_wptr = &cik_gfx_get_wptr,
.get_wptr = &cik_compute_get_wptr,
.get_wptr = &cik_sdma_get_wptr,
.get_wptr = &vce_v1_0_get_wptr,
.get_wptr = &r100_gfx_get_wptr,
.get_wptr = &r100_gfx_get_wptr,
.get_wptr = &r600_gfx_get_wptr,
.get_wptr = &r600_dma_get_wptr,