CIX_FIFO_UFLOW_INT
if (int_status & CIX_FIFO_UFLOW_INT) {
cix_mbox_write(priv, CIX_FIFO_UFLOW_INT, CIX_INT_CLEAR);
val |= CIX_FIFO_UFLOW_INT|CIX_FIFO_WM01_INT;
val &= ~(CIX_FIFO_UFLOW_INT | CIX_FIFO_WM01_INT);