fsl_readl
if (fsl_readl(&dr_regs->endptstatus) & bitmask)
while (fsl_readl(&dr_regs->endptflush)) {
} while (fsl_readl(&dr_regs->endptstatus) & bits);
return (int)(fsl_readl(&dr_regs->frindex) & USB_FRINDEX_MASKS);
portsc = fsl_readl(&dr_regs->portsc1);
fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
tmp = fsl_readl(&dr_regs->endptctrl[0]);
tmp = fsl_readl(&dr_regs->portsc1) | (ptc << 16);
temp = fsl_readl(&dr_regs->endptsetupstat);
temp = fsl_readl(&dr_regs->usbcmd);
} while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_SUTW));
temp = fsl_readl(&dr_regs->usbcmd);
bit_pos = fsl_readl(&dr_regs->endptcomplete);
if (!(fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET))
portscx_device_speed(fsl_readl(&dr_regs->portsc1));
temp = fsl_readl(&dr_regs->deviceaddr);
temp = fsl_readl(&dr_regs->endptsetupstat);
temp = fsl_readl(&dr_regs->endptcomplete);
while (fsl_readl(&dr_regs->endpointprime)) {
if (fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET) {
irq_src = fsl_readl(&dr_regs->usbsts) & fsl_readl(&dr_regs->usbintr);
if ((fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_SUSPEND) == 0)
if (fsl_readl(&dr_regs->endptsetupstat) & EP_SETUP_STATUS_EP0) {
if (fsl_readl(&dr_regs->endptcomplete)) {
tmp_reg = fsl_readl(&dr_regs->usbcmd);
tmp_reg = fsl_readl(&dr_regs->usbsts);
tmp_reg = fsl_readl(&dr_regs->usbintr);
tmp_reg = fsl_readl(&dr_regs->frindex);
tmp_reg = fsl_readl(&dr_regs->deviceaddr);
tmp_reg = fsl_readl(&dr_regs->endpointlistaddr);
tmp_reg = fsl_readl(&dr_regs->portsc1);
tmp_reg = fsl_readl(&dr_regs->usbmode);
tmp_reg = fsl_readl(&dr_regs->endptsetupstat);
tmp_reg = fsl_readl(&dr_regs->endptctrl[i]);
tmp_reg = fsl_readl(&dr_regs->endpointprime);
portctrl = fsl_readl(&dr_regs->portsc1);
dccparams = fsl_readl(&dr_regs->dccparams);
mode = fsl_readl(&dr_regs->usbmode) & USB_MODE_CTRL_MODE_MASK;
usbcmd = fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP;
tmp = fsl_readl(&dr_regs->usbcmd);
tmp = fsl_readl(&dr_regs->usbcmd);
while (fsl_readl(&dr_regs->usbcmd) & USB_CMD_CTRL_RESET) {
tmp = fsl_readl(&dr_regs->usbmode);
fsl_readl(&dr_regs->endpointlistaddr));
max_no_of_ep = (0x0000001F & fsl_readl(&dr_regs->dccparams));
tmp = fsl_readl(&dr_regs->endptctrl[ep_num]);
temp = fsl_readl(&dr_regs->usbmode);
temp = fsl_readl(&dr_regs->usbcmd);
if (!(fsl_readl(&dr_regs->otgsc) & OTGSC_STS_USB_ID)) {
tmp = fsl_readl(&dr_regs->usbcmd);
tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
if (fsl_readl(&dr_regs->endpointprime) & bitmask)
temp = fsl_readl(&dr_regs->usbcmd);
tmp_stat = fsl_readl(&dr_regs->endptstatus) & bitmask;
} while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_ATDTW));
temp = fsl_readl(&dr_regs->usbcmd);
epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
out: epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
tmp = fsl_readl(&usb_dr_regs->otgsc) & ~OTGSC_INTSTS_MASK;
tmp = fsl_readl(&usb_dr_regs->otgsc) & ~OTGSC_INTSTS_MASK;
tmp = fsl_readl(&usb_dr_regs->portsc) & ~PORTSC_W1C_BITS;
tmp = fsl_readl(&usb_dr_regs->portsc) &
tmp = fsl_readl(&usb_dr_regs->otgsc) & ~OTGSC_INTSTS_MASK;
tmp = fsl_readl(&fsl_otg_dev->dr_mem_map->portsc) & ~PORTSC_W1C_BITS;
tmp = fsl_readl(&usb_dr_regs->otgsc) & ~OTGSC_INTSTS_MASK;
command = fsl_readl(&usb_dr_regs->usbcmd);
while (fsl_readl(&usb_dr_regs->usbcmd) & (1 << 1))
!!(fsl_readl(&usb_dr_regs->otgsc) & OTGSC_STS_A_VBUS_VALID);
if (!(fsl_readl(&otg_dev->dr_mem_map->otgsc) &
otg_sc = fsl_readl(&usb_dr_regs->otgsc);
temp = fsl_readl(&p_otg->dr_mem_map->usbcmd);
temp = fsl_readl(&p_otg->dr_mem_map->usbcmd);
while (fsl_readl(&p_otg->dr_mem_map->usbcmd) & USB_CMD_CTRL_RESET)
temp = fsl_readl(&p_otg->dr_mem_map->portsc);
temp = fsl_readl(&p_otg->dr_mem_map->otgsc);
if (fsl_readl(&p_otg->dr_mem_map->otgsc) & OTGSC_STS_USB_ID) {
temp = fsl_readl(&p_otg->dr_mem_map->otgsc);