fpga_read_reg
version = fpga_read_reg(FPGAVR);
date = fpga_read_reg(FPGADR);
return !!(fpga_read_reg(USRGPIR) & (1 << gpio));
fpga_write_reg(fpga_read_reg(INTMSR) | 0x0303, INTMSR);
tmp = fpga_read_reg(INTAMR);
tmp = fpga_read_reg(NMISR);
tmp = fpga_read_reg(SBCR);
return fpga_read_reg(MODSWR);
fpga_write_reg(fpga_read_reg(PCIECR) | PCIECR_CLKEN, PCIECR);
fpga_write_reg(fpga_read_reg(PCIECR) & ~PCIECR_CLKEN, PCIECR);
fpga_write_reg(fpga_read_reg(PWRCR) | PWRCR_PDWNREQ, PWRCR);
while ((fpga_read_reg(PWRCR) & PWRCR_PDWNACK) == 0)
pr_info("\tPCB revision:\t%d\n", fpga_read_reg(PCBRR) & 0xf);
data = fpga_read_reg(LCLASR);
u16 data = fpga_read_reg(PCIECR);