fxp_q4_from_int
crtc_state->dsc.compressed_bpp_x16 = fxp_q4_from_int(min(crtc_state->pipe_bpp,
return fxp_q4_from_int(pipe_bpp);
return fxp_q4_from_int(1);
return fxp_q4_from_int(1);
return fxp_q4_from_int(1) / incr;
return fxp_q4_from_int(12);
min_bpp_x16 = fxp_q4_from_int(dsc_min_bpp);
max_link_bpp_x16 = min(max_link_bpp_x16, fxp_q4_from_int(dsc_max_bpp));
fxp_q4_from_int(limits->pipe.max_bpp));
max_link_bpp_x16 = rounddown(max_link_bpp_x16, fxp_q4_from_int(2 * 3));
if (max_link_bpp_x16 < fxp_q4_from_int(limits->pipe.min_bpp))
limits->link.min_bpp_x16 = fxp_q4_from_int(limits->pipe.min_bpp);
fxp_q4_from_int(crtc_state->pipe_bpp);
fxp_q4_from_int(pipe_config->pipe_bpp),
fxp_q4_from_int(pipe_config->pipe_bpp),
crtc_state->dsc.compressed_bpp_x16 < fxp_q4_from_int(8)));
int vesa_bpp_x16 = fxp_q4_from_int(valid_dsc_bpp[i]);
int vesa_bpp_x16 = fxp_q4_from_int(valid_dsc_bpp[i]);
fxp_q4_from_int(18), 0);
fxp_q4_from_int(min_bpp),
max_dpt_bpp_x16 = fxp_q4_from_int(intel_dp_mst_max_dpt_bpp(crtc_state, dsc));
fxp_q4_from_int(2 * 3), false);
if (limits->link.max_bpp_x16 < fxp_q4_from_int(24))
limits->link.min_bpp_x16 = fxp_q4_from_int(24);
min_bpp_x16 = fxp_q4_from_int(13);
min_bpp_x16 = fxp_q4_from_int(10);
intel_link_compute_m_n(fxp_q4_from_int(pipe_config->pipe_bpp),
link_bpp_x16 = fxp_q4_from_int(crtc_state->pipe_bpp);
*val_x16 = fxp_q4_from_int(val);
(bpp_x16 < fxp_q4_from_int(min_bpp) ||
bpp_x16 > fxp_q4_from_int(intel_display_max_pipe_bpp(display))))