fm10k_write_reg
fm10k_write_reg(hw, FM10K_TXDCTL(i),
fm10k_write_reg(hw, FM10K_RXQCTL(i),
fm10k_write_reg(hw, FM10K_RSSRK(0, i), rssrk);
fm10k_write_reg(hw, FM10K_MRQC(0), mrqc);
fm10k_write_reg(hw, FM10K_RETA(0, i), reta);
fm10k_write_reg(hw, FM10K_DGLORTMAP(fm10k_dglort_vf_rss),
fm10k_write_reg(hw, mbx->mbx_reg, FM10K_MBX_REQ |
fm10k_write_reg(hw, mbx->mbmem_reg, 0);
fm10k_write_reg(hw, mbx->mbmem_reg ^ mbx->mbmem_len, mbx->mbx_hdr);
fm10k_write_reg(hw, mbx->mbx_reg, FM10K_MBX_REQ |
fm10k_write_reg(hw, mbx->mbmem_reg, 0);
fm10k_write_reg(hw, mbmem + tail++, *(head++));
fm10k_write_reg(hw, mbx->mbx_reg,
fm10k_write_reg(hw, mbmem, mbx->mbx_hdr);
fm10k_write_reg(hw, mbx->mbx_reg, mbx->mbx_lock);
fm10k_write_reg(hw, FM10K_TUNNEL_CFG,
fm10k_write_reg(hw, FM10K_TUNNEL_CFG_GENEVE,
fm10k_write_reg(hw, FM10K_RDLEN(reg_idx), size);
fm10k_write_reg(hw, FM10K_RDH(reg_idx), 0);
fm10k_write_reg(hw, FM10K_RDT(reg_idx), 0);
fm10k_write_reg(hw, FM10K_SRRCTL(reg_idx), srrctl);
fm10k_write_reg(hw, FM10K_RXDCTL(reg_idx), rxdctl);
fm10k_write_reg(hw, FM10K_RXINT(reg_idx), rxint);
fm10k_write_reg(hw, FM10K_RXQCTL(reg_idx), rxqctl);
fm10k_write_reg(hw, FM10K_RXDCTL(reg_idx), rxdctl);
fm10k_write_reg(hw, FM10K_RSSRK(0, i), interface->rssrk[i]);
fm10k_write_reg(hw, FM10K_RETA(0, i), interface->reta[i]);
fm10k_write_reg(hw, FM10K_MRQC(0), mrqc);
fm10k_write_reg(hw, FM10K_VFITR(FM10K_MBX_VECTOR),
fm10k_write_reg(hw, FM10K_MAXHOLDQ(7), maxholdq);
fm10k_write_reg(hw, FM10K_RXDCTL(q), rxdctl);
fm10k_write_reg(hw, FM10K_MAXHOLDQ(q / 32), maxholdq);
fm10k_write_reg(hw, FM10K_EICR, eicr & (FM10K_EICR_MAILBOX |
fm10k_write_reg(hw, FM10K_ITR(FM10K_MBX_VECTOR),
fm10k_write_reg(hw, FM10K_EIMR,
fm10k_write_reg(hw, itr_reg, FM10K_ITR_MASK_SET);
fm10k_write_reg(hw, FM10K_VFINT_MAP, itr);
fm10k_write_reg(hw, FM10K_VFITR(entry->entry), FM10K_ITR_ENABLE);
fm10k_write_reg(hw, FM10K_INT_MAP(fm10k_int_pcie_fault), other_itr);
fm10k_write_reg(hw, FM10K_INT_MAP(fm10k_int_switch_up_down), other_itr);
fm10k_write_reg(hw, FM10K_INT_MAP(fm10k_int_sram), other_itr);
fm10k_write_reg(hw, FM10K_INT_MAP(fm10k_int_max_hold_time), other_itr);
fm10k_write_reg(hw, FM10K_INT_MAP(fm10k_int_vflr), other_itr);
fm10k_write_reg(hw, FM10K_INT_MAP(fm10k_int_mailbox), mbx_itr);
fm10k_write_reg(hw, FM10K_EIMR, FM10K_EIMR_ENABLE(PCA_FAULT) |
fm10k_write_reg(hw, FM10K_ITR(entry->entry), FM10K_ITR_ENABLE);
fm10k_write_reg(hw, FM10K_SWPRI_MAP(i),
fm10k_write_reg(hw, FM10K_TXDCTL(reg_idx), 0);
fm10k_write_reg(hw, FM10K_TDBAL(reg_idx), tdba & DMA_BIT_MASK(32));
fm10k_write_reg(hw, FM10K_TDBAH(reg_idx), tdba >> 32);
fm10k_write_reg(hw, FM10K_TDLEN(reg_idx), size);
fm10k_write_reg(hw, FM10K_TDH(reg_idx), 0);
fm10k_write_reg(hw, FM10K_TDT(reg_idx), 0);
fm10k_write_reg(hw, FM10K_TXINT(reg_idx), txint);
fm10k_write_reg(hw, FM10K_PFVTCTL(reg_idx),
fm10k_write_reg(hw, FM10K_TXDCTL(reg_idx), txdctl);
fm10k_write_reg(hw, FM10K_RXQCTL(reg_idx), rxqctl);
fm10k_write_reg(hw, FM10K_RDBAL(reg_idx), rdba & DMA_BIT_MASK(32));
fm10k_write_reg(hw, FM10K_RDBAH(reg_idx), rdba >> 32);
fm10k_write_reg(hw, FM10K_ITR2(0), 0);
fm10k_write_reg(hw, FM10K_RXQCTL(i), rxqctl);
fm10k_write_reg(hw, FM10K_TC_MAXCREDIT(vf_idx), 0);
fm10k_write_reg(hw, FM10K_TC_RATE(vf_idx), 0);
fm10k_write_reg(hw, FM10K_TC_CREDIT(vf_idx),
fm10k_write_reg(hw, FM10K_ITR2(0), vf_v_idx);
fm10k_write_reg(hw, FM10K_ITR2(vf_v_limit), vf_v_idx);
fm10k_write_reg(hw, FM10K_ITR2(vf_v_idx), vf_v_idx - 1);
fm10k_write_reg(hw, FM10K_MBMEM_VF(vf_idx, i), 0);
fm10k_write_reg(hw, FM10K_ITR2(FM10K_ITR_REG_COUNT_PF), 0);
fm10k_write_reg(hw, FM10K_VLAN_TABLE(vf_info->vsi, i), 0);
fm10k_write_reg(hw, FM10K_RETA(vf_info->vsi, i), 0);
fm10k_write_reg(hw, FM10K_RSSRK(vf_info->vsi, i), 0);
fm10k_write_reg(hw, FM10K_MRQC(vf_info->vsi), 0);
fm10k_write_reg(hw, FM10K_TDBAL(vf_q_idx + i), tdbal);
fm10k_write_reg(hw, FM10K_TDBAH(vf_q_idx + i), tdbah);
fm10k_write_reg(hw, FM10K_TDLEN(vf_q_idx + i),
fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx + i), vf_q_idx + i);
fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx + i), vf_q_idx + i);
fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx + i), vf_q_idx);
fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx + i), vf_q_idx);
fm10k_write_reg(hw, FM10K_ITR2(i), i - 1);
fm10k_write_reg(hw, FM10K_INT_CTRL, FM10K_INT_CTRL_ENABLEMODERATOR);
fm10k_write_reg(hw, FM10K_TQDLOC(i),
fm10k_write_reg(hw, FM10K_TXQCTL(i), txqctl);
fm10k_write_reg(hw, FM10K_TPH_TXCTRL(i),
fm10k_write_reg(hw, FM10K_TPH_RXCTRL(i),
fm10k_write_reg(hw, FM10K_PHYADDR, phyaddr);
fm10k_write_reg(hw, type + FM10K_FAULT_FUNC, FM10K_FAULT_FUNC_VALID);
fm10k_write_reg(hw, FM10K_DTXTCPFLGL, FM10K_TSO_FLAGS_LOW);
fm10k_write_reg(hw, FM10K_DTXTCPFLGH, FM10K_TSO_FLAGS_HI);
fm10k_write_reg(hw, FM10K_DMA_CTRL, dma_ctrl);
fm10k_write_reg(hw, FM10K_EIMR, FM10K_EIMR_DISABLE(ALL));
fm10k_write_reg(hw, reg, vlan_table ^ mask);
fm10k_write_reg(hw, FM10K_ITR2(0), 0);
fm10k_write_reg(hw, FM10K_INT_CTRL, 0);
fm10k_write_reg(hw, FM10K_TQMAP(i), 0);
fm10k_write_reg(hw, FM10K_RQMAP(i), 0);
fm10k_write_reg(hw, FM10K_INT_CTRL, 0);
fm10k_write_reg(hw, FM10K_ITR2(FM10K_ITR_REG_COUNT_PF), i);
fm10k_write_reg(hw, FM10K_ITR2(0), i);
fm10k_write_reg(hw, FM10K_INT_CTRL, FM10K_INT_CTRL_ENABLEMODERATOR);
fm10k_write_reg(hw, FM10K_TX_SGLORT(q_idx), glort);
fm10k_write_reg(hw, FM10K_RX_SGLORT(q_idx), glort);
fm10k_write_reg(hw, FM10K_DMA_CTRL, reg);
fm10k_write_reg(hw, FM10K_TXQCTL(q_idx), txqctl);
fm10k_write_reg(hw, FM10K_DGLORTDEC(dglort->idx), dglortdec);
fm10k_write_reg(hw, FM10K_DGLORTMAP(dglort->idx), dglortmap);
fm10k_write_reg(hw, FM10K_TC_MAXCREDIT(i), 0);
fm10k_write_reg(hw, FM10K_TC_RATE(i), 0);
fm10k_write_reg(hw, FM10K_TC_CREDIT(i),
fm10k_write_reg(hw, FM10K_MBMEM(i), 0);
fm10k_write_reg(hw, FM10K_PFVFLREC(0), ~0);
fm10k_write_reg(hw, FM10K_PFVFLREC(1), ~0);
fm10k_write_reg(hw, FM10K_TXDCTL(i), 0);
fm10k_write_reg(hw, FM10K_TXQCTL(i), FM10K_TXQCTL_PF |
fm10k_write_reg(hw, FM10K_RXQCTL(i), FM10K_RXQCTL_PF);
fm10k_write_reg(hw, FM10K_ITR2(i), i - vpp);
fm10k_write_reg(hw, FM10K_ITR2(i), i - 1);
fm10k_write_reg(hw, FM10K_ITR2(0),
fm10k_write_reg(hw, FM10K_TXDCTL(vf_q_idx), 0);
fm10k_write_reg(hw, FM10K_TXQCTL(vf_q_idx),
fm10k_write_reg(hw, FM10K_RXDCTL(vf_q_idx),
fm10k_write_reg(hw, FM10K_RXQCTL(vf_q_idx),
fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), vf_q_idx);
fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx), vf_q_idx);
fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), vf_q_idx0);
fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx), vf_q_idx0);
fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), 0);
fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx), 0);
fm10k_write_reg(hw, FM10K_TC_RATE(vf_idx), tc_rate | interval);
fm10k_write_reg(hw, FM10K_TC_MAXCREDIT(vf_idx), FM10K_TC_MAXCREDIT_64K);
fm10k_write_reg(hw, FM10K_TC_CREDIT(vf_idx), FM10K_TC_MAXCREDIT_64K);
fm10k_write_reg(hw, FM10K_ITR2(0), i);
fm10k_write_reg(hw, FM10K_ITR2(vf_v_limit), i);
fm10k_write_reg(hw, FM10K_TXQCTL(vf_q_idx + i), txqctl);
fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), 0);
fm10k_write_reg(hw, FM10K_TXDCTL(vf_q_idx), 0);
fm10k_write_reg(hw, FM10K_DGLORTDEC(fm10k_dglort_default), 0);
fm10k_write_reg(hw, FM10K_DGLORTMAP(fm10k_dglort_default),
fm10k_write_reg(hw, FM10K_TDBAL(vf_q_idx), tdbal);
fm10k_write_reg(hw, FM10K_TDBAH(vf_q_idx), tdbah);
fm10k_write_reg(hw, FM10K_TDLEN(vf_q_idx), hw->mac.itr_scale <<
fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), vf_q_idx);
fm10k_write_reg(hw, FM10K_PFVFLREC(vf_idx / 32), BIT(vf_idx % 32));
fm10k_write_reg(hw, FM10K_DGLORTMAP(i), FM10K_DGLORTMAP_NONE);
fm10k_write_reg(hw, FM10K_TQMAP(i), 0);
fm10k_write_reg(hw, FM10K_RQMAP(i), 0);
fm10k_write_reg(hw, FM10K_TXDCTL(i), 0);
fm10k_write_reg(hw, FM10K_TXQCTL(i), txqctl);
fm10k_write_reg(hw, FM10K_RXDCTL(i),
fm10k_write_reg(hw, FM10K_TDBAL(i), bal);
fm10k_write_reg(hw, FM10K_TDBAH(i), bah);
fm10k_write_reg(hw, FM10K_RDBAL(i), bal);
fm10k_write_reg(hw, FM10K_RDBAH(i), bah);
fm10k_write_reg(hw, FM10K_TDLEN(i), tdlen);
fm10k_write_reg(hw, FM10K_VFCTRL, FM10K_VFCTRL_RST);
fm10k_write_reg(hw, FM10K_VFCTRL, 0);