arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c

100

CI(irq_positive, EDGE_IS_POSITIVE);

arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c

102

CI(area_optimised, AREA_OPTIMISED);

arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c

104

CI(hw_debug, DEBUG_ENABLED);

arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c

105

CI(num_pc_brk, NUMBER_OF_PC_BRK);

arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c

106

CI(num_rd_brk, NUMBER_OF_RD_ADDR_BRK);

arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c

107

CI(num_wr_brk, NUMBER_OF_WR_ADDR_BRK);

arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c

109

CI(fpga_family_code, TARGET_FAMILY);

arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c

34

CI(ver_code, VERSION);

arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c

65

CI(pvr_user1, USER1);

arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c

66

CI(pvr_user2, USER2);

arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c

68

CI(mmu, USE_MMU);

arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c

69

CI(mmu_privins, MMU_PRIVINS);

arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c

70

CI(endian, ENDIAN);

arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c

72

CI(use_icache, USE_ICACHE);

arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c

73

CI(icache_tagbits, ICACHE_ADDR_TAG_BITS);

arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c

74

CI(icache_write, ICACHE_ALLOW_WR);

arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c

76

CI(icache_size, ICACHE_BYTE_SIZE);

arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c

77

CI(icache_base, ICACHE_BASEADDR);

arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c

78

CI(icache_high, ICACHE_HIGHADDR);

arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c

80

CI(use_dcache, USE_DCACHE);

arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c

81

CI(dcache_tagbits, DCACHE_ADDR_TAG_BITS);

arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c

82

CI(dcache_write, DCACHE_ALLOW_WR);

arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c

84

CI(dcache_size, DCACHE_BYTE_SIZE);

arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c

85

CI(dcache_base, DCACHE_BASEADDR);

arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c

86

CI(dcache_high, DCACHE_HIGHADDR);

arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c

93

CI(use_dopb, D_OPB);

arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c

94

CI(use_iopb, I_OPB);

arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c

95

CI(use_dlmb, D_LMB);

arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c

96

CI(use_ilmb, I_LMB);

arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c

97

CI(num_fsl, FSL_LINKS);

arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c

99

CI(irq_edge, INTERRUPT_IS_EDGE);

drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.c

722

HINIC_CMDQ_CTXT_BLOCK_INFO_SET(atomic_read(&wq->cons_idx), CI);

drivers/net/ethernet/huawei/hinic/hinic_hw_qp.c

141

HINIC_SQ_CTXT_PREF_SET(ci_start, CI) |

drivers/net/ethernet/huawei/hinic/hinic_hw_qp.c

185

HINIC_RQ_CTXT_WQ_PAGE_SET(ci_start, CI);

drivers/net/ethernet/huawei/hinic/hinic_hw_qp.c

198

HINIC_RQ_CTXT_PREF_SET(ci_start, CI);

drivers/net/ethernet/huawei/hinic3/hinic3_cmdq.c

602

ctxt_info->wq_block_pfn = cpu_to_le64(CMDQ_CTXT_SET(wq->cons_idx, CI) |

drivers/net/ethernet/huawei/hinic3/hinic3_eqs.c

166

EQ_CI_SIMPLE_INDIR_SET(eq_wrap_ci, CI) |

drivers/net/ethernet/huawei/hinic3/hinic3_eqs.c

170

EQ_CI_SIMPLE_INDIR_SET(eq_wrap_ci, CI) |