for_each_set_bit_from
for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) {
for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) {
for_each_set_bit_from(bit, (unsigned long *)&(mask), 8 * sizeof(mask))
for_each_set_bit_from(vec, pir_copy, FIRST_SYSTEM_VECTOR)
for_each_set_bit_from(st_offset, etnaviv_states, size) {
for_each_set_bit_from(bit, &supported,
for_each_set_bit_from(gpio_nr, mask, ADM1266_GPIO_NR + ADM1266_PDIO_STATUS) {
for_each_set_bit_from(bit, interrupt_bits,
for_each_set_bit_from(pg_shift, &cap, sizeof(cap) * BITS_PER_BYTE) {
for_each_set_bit_from(bit, bm, max_bit)
for_each_set_bit_from(bit, &status, max) {
for_each_set_bit_from(bit, &status, max) {
for_each_set_bit_from(pos, &val, size) {
for_each_set_bit_from(index, priv->cfp.unique, priv->num_cfp_rules) {
for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID)
for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID)
for_each_set_bit_from(bitnr, (unsigned long *)&masked_cfg, NPC_EXACT_NIBBLE_END + 1) {
for_each_set_bit_from(vid, wx->active_vlans, VLAN_N_VID)
for_each_set_bit_from(i, callid_bitmap, MAX_CALLID) {
for_each_set_bit_from(idx, valid_bits,
for_each_set_bit_from(irq_bit, &status, PCI_NUM_INTX +
for_each_set_bit_from(irq_bit, &status, PCIE_MSI_SET_NUM +
for_each_set_bit_from(bit, &status, PCI_NUM_INTX + INTX_SHIFT) {
for_each_set_bit_from(i, drv->tcs_in_use, tcs->offset + tcs->num_tcs) {
for_each_set_bit_from(i, bitmap_info->bitmap, BITS_PER_BITMAP) {
for_each_set_bit_from(i, entry->bitmap, BITS_PER_BITMAP) {
for_each_set_bit_from(bit, bfs->bitmaps, start_bit + nbits) {
for_each_set_bit_from(i, &zwsm->active_map, ZSTD_BTRFS_MAX_LEVEL) {
for_each_set_bit_from(bit, addr, max + 1) {
for_each_set_bit_from(segno, bitmap, end) {
for_each_set_bit_from(cpu, cpumask_bits(mask), small_cpumask_bits)
for_each_set_bit_from(bit, orig, 500)
for_each_set_bit_from(bit, &mcasp->pdir, PIN_BIT_AFSR + 1) {
for_each_set_bit_from(bit, &mcasp->pdir, bit_end) {