fault_info
const struct fault_info *inf = esr_to_fault_info(esr);
static const struct fault_info fault_info[];
static inline const struct fault_info *esr_to_fault_info(unsigned long esr)
const struct fault_info *inf;
return fault_info + (esr & ESR_ELx_FSC);
const struct fault_info *inf;
static const struct fault_info fault_info[] = {
const struct fault_info *inf = esr_to_fault_info(esr);
struct hv_fault_status fault_info;
hdesc->fault_info_va = (unsigned long) &tb->fault_info;
hdesc->fault_info_pa = kimage_addr_to_ra(&tb->fault_info);
offsetof(struct trap_per_cpu, fault_info)) ||
cr->status, cr->result, cr->fault_info, cr->bytes_completed,
struct amdgpu_vm_fault_info *fault_info;
fault_info = &coredump->adev->vm_manager.fault_info;
fault_info->vmhub ? "mmhub" : "gfxhub");
drm_printf(&p, "Faulty page starting at address: 0x%016llx\n", fault_info->addr);
drm_printf(&p, "Protection fault status register: 0x%x\n\n", fault_info->status);
gpuvm_fault.addr = vm->fault_info.addr;
gpuvm_fault.status = vm->fault_info.status;
gpuvm_fault.vmhub = vm->fault_info.vmhub;
vm->fault_info.addr = addr;
vm->fault_info.status = status;
adev->vm_manager.fault_info.addr = addr;
adev->vm_manager.fault_info.vmhub = vmhub;
adev->vm_manager.fault_info.status = status;
vm->fault_info.vmhub = AMDGPU_VMHUB_TYPE_GFX;
vm->fault_info.vmhub |=
vm->fault_info.vmhub = AMDGPU_VMHUB_TYPE_MM0;
vm->fault_info.vmhub |=
vm->fault_info.vmhub = AMDGPU_VMHUB_TYPE_MM1;
vm->fault_info.vmhub |=
struct amdgpu_vm_fault_info fault_info;
struct amdgpu_vm_fault_info fault_info;
struct rogue_fw_fault_info fault_info[ROGUE_FWIF_FWFAULTINFO_MAX];
OFFSET_CHECK(struct rogue_fwif_sysdata, fault_info, 80);
struct msm_gpu_fault_info fault_info = {};
fault_info.ttbr0 = info->ttbr0;
fault_info.iova = iova;
fault_info.flags = flags;
fault_info.type = type;
fault_info.block = block;
msm_gpu_fault_crashstate_capture(gpu, &fault_info);
if (state->fault_info.ttbr0) {
const struct msm_gpu_fault_info *info = &state->fault_info;
struct msm_gem_submit *submit, struct msm_gpu_fault_info *fault_info,
if (fault_info)
state->fault_info = *fault_info;
if (submit && state->fault_info.ttbr0) {
struct msm_gpu_fault_info *info = &state->fault_info;
struct msm_gem_submit *submit, struct msm_gpu_fault_info *fault_info,
void msm_gpu_fault_crashstate_capture(struct msm_gpu *gpu, struct msm_gpu_fault_info *fault_info)
msm_gpu_crashstate_capture(gpu, submit, fault_info, comm, cmd);
struct msm_gpu_fault_info fault_info;
void msm_gpu_fault_crashstate_capture(struct msm_gpu *gpu, struct msm_gpu_fault_info *fault_info);
u64 fault_info;
info = cs_iface->output->fault_info;
u32 fault_info; /* fault transaction info */
u32 info = readl(SYSMMU_REG(data, fault_info));
.fault_info = 0x78,
.fault_info = 0x1004,
__le32 fault_info[3];
code1 = readl(&mrioc->sysif_regs->fault_info[0]);
code2 = readl(&mrioc->sysif_regs->fault_info[1]);
code3 = readl(&mrioc->sysif_regs->fault_info[2]);
readl(&mrioc->sysif_regs->fault_info[i]);
struct f2fs_fault_info *ffi = &F2FS_OPTION(sbi).fault_info;
struct f2fs_fault_info fault_info; /* For fault injection */
struct f2fs_fault_info *ffi = &F2FS_OPTION(sbi).fault_info;
F2FS_CTX_INFO(ctx).fault_info.inject_rate, 0, FAULT_RATE);
F2FS_CTX_INFO(ctx).fault_info.inject_type, FAULT_TYPE);
F2FS_OPTION(sbi).fault_info.inject_rate);
F2FS_OPTION(sbi).fault_info.inject_type);
struct f2fs_fault_info *ffi = &F2FS_OPTION(sbi).fault_info;
F2FS_CTX_INFO(ctx).fault_info.inject_rate = result.int_32;
F2FS_CTX_INFO(ctx).fault_info.inject_type = result.uint_32;
struct f2fs_fault_info *ffi = &F2FS_OPTION(sbi).fault_info;
return (unsigned char *)&F2FS_OPTION(sbi).fault_info;
__u8 fault_info;
__u8 fault_info;