fm10k_read_reg
reg = fm10k_read_reg(hw, FM10K_TXDCTL(i));
reg = fm10k_read_reg(hw, FM10K_RXQCTL(i));
reg = fm10k_read_reg(hw, FM10K_TXDCTL(i));
reg = fm10k_read_reg(hw, FM10K_RXQCTL(i));
u32 delta = fm10k_read_reg(hw, addr) - stat->base_l;
count_h = fm10k_read_reg(hw, addr + 1);
count_l = fm10k_read_reg(hw, addr);
count_h = fm10k_read_reg(hw, addr + 1);
id_tx = fm10k_read_reg(hw, FM10K_TXQCTL(idx));
id_tx = fm10k_read_reg(hw, FM10K_TXQCTL(idx));
id_rx = fm10k_read_reg(hw, FM10K_RXQCTL(idx));
id_rx = fm10k_read_reg(hw, FM10K_RXQCTL(idx));
u32 txdctl = fm10k_read_reg(hw, FM10K_TXDCTL(0));
u32 fm10k_read_reg(struct fm10k_hw *hw, int reg);
#define fm10k_write_flush(hw) fm10k_read_reg((hw), FM10K_CTRL)
buff[idx++] = fm10k_read_reg(hw, FM10K_RDBAL(i));
buff[idx++] = fm10k_read_reg(hw, FM10K_RDBAH(i));
buff[idx++] = fm10k_read_reg(hw, FM10K_RDLEN(i));
buff[idx++] = fm10k_read_reg(hw, FM10K_TPH_RXCTRL(i));
buff[idx++] = fm10k_read_reg(hw, FM10K_RDH(i));
buff[idx++] = fm10k_read_reg(hw, FM10K_RDT(i));
buff[idx++] = fm10k_read_reg(hw, FM10K_RXQCTL(i));
buff[idx++] = fm10k_read_reg(hw, FM10K_RXDCTL(i));
buff[idx++] = fm10k_read_reg(hw, FM10K_RXINT(i));
buff[idx++] = fm10k_read_reg(hw, FM10K_SRRCTL(i));
buff[idx++] = fm10k_read_reg(hw, FM10K_QPRC(i));
buff[idx++] = fm10k_read_reg(hw, FM10K_QPRDC(i));
buff[idx++] = fm10k_read_reg(hw, FM10K_QBRC_L(i));
buff[idx++] = fm10k_read_reg(hw, FM10K_QBRC_H(i));
buff[idx++] = fm10k_read_reg(hw, FM10K_TDBAL(i));
buff[idx++] = fm10k_read_reg(hw, FM10K_TDBAH(i));
buff[idx++] = fm10k_read_reg(hw, FM10K_TDLEN(i));
buff[idx++] = fm10k_read_reg(hw, FM10K_TPH_TXCTRL(i));
buff[idx++] = fm10k_read_reg(hw, FM10K_TDH(i));
buff[idx++] = fm10k_read_reg(hw, FM10K_TDT(i));
buff[idx++] = fm10k_read_reg(hw, FM10K_TXDCTL(i));
buff[idx++] = fm10k_read_reg(hw, FM10K_TXQCTL(i));
buff[idx++] = fm10k_read_reg(hw, FM10K_TXINT(i));
buff[idx++] = fm10k_read_reg(hw, FM10K_QPTC(i));
buff[idx++] = fm10k_read_reg(hw, FM10K_QBTC_L(i));
buff[idx++] = fm10k_read_reg(hw, FM10K_QBTC_H(i));
buff[idx++] = fm10k_read_reg(hw, FM10K_TQDLOC(i));
buff[idx++] = fm10k_read_reg(hw, FM10K_TX_SGLORT(i));
buff[idx++] = fm10k_read_reg(hw, FM10K_PFVTCTL(i));
buff[idx++] = fm10k_read_reg(hw, FM10K_MRQC(i));
buff[idx++] = fm10k_read_reg(hw, FM10K_RSSRK(i, j));
buff[idx++] = fm10k_read_reg(hw, FM10K_RETA(i, j));
*(buff++) = fm10k_read_reg(hw, FM10K_CTRL);
*(buff++) = fm10k_read_reg(hw, FM10K_CTRL_EXT);
*(buff++) = fm10k_read_reg(hw, FM10K_GCR);
*(buff++) = fm10k_read_reg(hw, FM10K_GCR_EXT);
*(buff++) = fm10k_read_reg(hw, FM10K_DGLORTMAP(i));
*(buff++) = fm10k_read_reg(hw, FM10K_DGLORTDEC(i));
*(buff++) = fm10k_read_reg(hw, FM10K_DMA_CTRL);
*(buff++) = fm10k_read_reg(hw, FM10K_DMA_CTRL2);
*(buff++) = fm10k_read_reg(hw, FM10K_TPH_CTRL);
*(buff++) = fm10k_read_reg(hw, FM10K_INT_MAP(i));
*(buff++) = fm10k_read_reg(hw, FM10K_ITR(i));
*(buff++) = fm10k_read_reg(hw, FM10K_VFCTRL);
*(buff++) = fm10k_read_reg(hw, FM10K_VFINT_MAP);
*(buff++) = fm10k_read_reg(hw, FM10K_VFSYSTIME);
*(buff++) = fm10k_read_reg(hw, FM10K_VFITR(i));
if (!(fm10k_read_reg(hw, FM10K_EICR) & FM10K_EICR_VFLR))
vflre = fm10k_read_reg(hw, FM10K_PFVFLRE(1));
vflre |= fm10k_read_reg(hw, FM10K_PFVFLRE(0));
head = fm10k_read_reg(hw, FM10K_TDH(ring->reg_idx));
tail = fm10k_read_reg(hw, FM10K_TDT(ring->reg_idx));
fm10k_read_reg(hw, FM10K_TDH(tx_ring->reg_idx)),
fm10k_read_reg(hw, FM10K_TDT(tx_ring->reg_idx)),
*(tail++) = fm10k_read_reg(hw, mbmem + head++);
if (fm10k_read_reg(hw, mbx->mbx_reg) & FM10K_MBX_REQ_INTERRUPT)
mbx->mbx_hdr = fm10k_read_reg(hw, mbx->mbmem_reg ^ mbx->mbmem_len);
rxqctl = fm10k_read_reg(hw, FM10K_RXQCTL(reg_idx));
maxholdq = fm10k_read_reg(hw, FM10K_MAXHOLDQ(7));
maxholdq = fm10k_read_reg(hw, FM10K_MAXHOLDQ(q / 32));
eicr = fm10k_read_reg(hw, FM10K_EICR);
if (fm10k_read_reg(hw, FM10K_TXDCTL(reg_idx)) & FM10K_TXDCTL_ENABLE)
txdctl = fm10k_read_reg(hw, FM10K_TXDCTL(reg_idx));
rxqctl = fm10k_read_reg(hw, FM10K_RXQCTL(reg_idx));
id = fm10k_read_reg(hw, FM10K_TXQCTL(0));
id = fm10k_read_reg(hw, FM10K_TXQCTL(0));
func = fm10k_read_reg(hw, type + FM10K_FAULT_FUNC);
fault->address = fm10k_read_reg(hw, type + FM10K_FAULT_ADDR_HI);
fault->address |= fm10k_read_reg(hw, type + FM10K_FAULT_ADDR_LO);
fault->specinfo = fm10k_read_reg(hw, type + FM10K_FAULT_SPECINFO);
dma_ctrl2 = fm10k_read_reg(hw, FM10K_DMA_CTRL2);
vlan_table = fm10k_read_reg(hw, reg);
serial_num = fm10k_read_reg(hw, FM10K_SM_AREA(1));
serial_num = fm10k_read_reg(hw, FM10K_SM_AREA(0));
if (!fm10k_read_reg(hw, FM10K_MSIX_VECTOR_MASK(i)))
reg = fm10k_read_reg(hw, FM10K_DMA_CTRL);
txqctl = fm10k_read_reg(hw, FM10K_TXQCTL(q_idx));
reg = fm10k_read_reg(hw, FM10K_IP);
if (!fm10k_read_reg(hw, FM10K_MSIX_VECTOR_MASK(i)))
txdctl = fm10k_read_reg(hw, FM10K_TXDCTL(vf_q_idx));
txdctl = fm10k_read_reg(hw, FM10K_TXDCTL(vf_q_idx));
if (!~fm10k_read_reg(hw, FM10K_TXQCTL(0)) ||
!~fm10k_read_reg(hw, FM10K_RXQCTL(0))) {
tqdloc = ~fm10k_read_reg(hw, FM10K_TQDLOC(i));
if (!~fm10k_read_reg(hw, FM10K_TXQCTL(i)) ||
!~fm10k_read_reg(hw, FM10K_RXQCTL(i)))
fm10k_read_reg(hw, FM10K_TXQCTL(0)));
fm10k_read_reg(hw, FM10K_TDLEN(0)));
base_addr = fm10k_read_reg(hw, FM10K_TDBAL(0));
base_addr = fm10k_read_reg(hw, FM10K_TDBAH(0));
if (fm10k_read_reg(hw, FM10K_VFCTRL) & FM10K_VFCTRL_RST)
u32 tqdloc, tqdloc0 = ~fm10k_read_reg(hw, FM10K_TQDLOC(0));