arch/arm/mach-exynos/firmware.c

124

exynos_smc(SMC_CMD_SLEEP, 0, 0, 0);

arch/arm/mach-exynos/firmware.c

171

exynos_smc(SMC_CMD_L2X0INVALL, 0, 0, 0);

arch/arm/mach-exynos/firmware.c

177

exynos_smc(SMC_CMD_L2X0CTRL, val, 0, 0);

arch/arm/mach-exynos/firmware.c

181

exynos_smc(SMC_CMD_L2X0DEBUG, val, 0, 0);

arch/arm/mach-exynos/firmware.c

191

exynos_smc(SMC_CMD_L2X0SETUP1, regs->tag_latency, regs->data_latency,

arch/arm/mach-exynos/firmware.c

193

exynos_smc(SMC_CMD_L2X0SETUP2, regs->pwr_ctrl, regs->aux_ctrl, 0);

arch/arm/mach-exynos/firmware.c

45

exynos_smc(SMC_CMD_SAVE, OP_TYPE_CORE,

arch/arm/mach-exynos/firmware.c

47

exynos_smc(SMC_CMD_SHUTDOWN, OP_TYPE_CLUSTER,

arch/arm/mach-exynos/firmware.c

50

exynos_smc(SMC_CMD_CPU0AFTR, 0, 0, 0);

arch/arm/mach-exynos/firmware.c

53

exynos_smc(SMC_CMD_SLEEP, 0, 0, 0);

arch/arm/mach-exynos/firmware.c

78

exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0);

arch/arm/mach-exynos/smc.h

37

extern void exynos_smc(u32 cmd, u32 arg1, u32 arg2, u32 arg3);

arch/arm/mach-exynos/suspend.c

347

exynos_smc(SMC_CMD_REG, SMC_REG_ID_SFR_W(pm_state.sysram_phys +

arch/arm/mach-exynos/suspend.c

489

exynos_smc(SMC_CMD_REG,