extclk_rate
to_settle_delay(sensor->pll->extclk_rate), &ret);
u64 extclk_rate, system_clk;
extclk_rate = clk_get_rate(sensor->extclk);
if (!extclk_rate)
imx111_pll[i].extclk_rate) {
extclk_rate);
system_clk = div_u64(extclk_rate, sensor->pll->pre_div) *
u64 extclk_rate;
{ .extclk_rate = 6000000, .pre_div = 1, .mult = 113, },
{ .extclk_rate = 12000000, .pre_div = 2, .mult = 113, },
{ .extclk_rate = 13500000, .pre_div = 1, .mult = 50, },
{ .extclk_rate = 18000000, .pre_div = 2, .mult = 75, },
{ .extclk_rate = 24000000, .pre_div = 4, .mult = 113, },
{ .extclk_rate = 27000000, .pre_div = 2, .mult = 50, },
{ .extclk_rate = 36000000, .pre_div = 4, .mult = 75, },
{ .extclk_rate = 54000000, .pre_div = 4, .mult = 50, },
static u8 to_settle_delay(u64 extclk_rate)
u64 extclk_mhz = div_u64(extclk_rate, MEGA);
pll1_rate = sensor->extclk_rate * config->pll_mul / config->pll_pre_div_half;
sensor->extclk_rate = clk_get_rate(sensor->extclk);
if (sensor->extclk_rate == supported_extclk_rates[i])
sensor->extclk_rate);
unsigned long extclk_rate;