ffreg_t
ffreg_t idlehead_high; /* Idle cell header (high) */
ffreg_t idlehead_low; /* Idle cell header (low) */
ffreg_t maxrate; /* Maximum rate */
ffreg_t stparms; /* Traffic Management Parameters */
ffreg_t abrubr_abr; /* ABRUBR Priority Byte 1, TCR Byte 0 */
ffreg_t rm_type; /* */
ffreg_t cmd_reg; /* Command register */
ffreg_t cbr_base; /* CBR Pointer Base */
ffreg_t vbr_base; /* VBR Pointer Base */
ffreg_t abr_base; /* ABR Pointer Base */
ffreg_t ubr_base; /* UBR Pointer Base */
ffreg_t vbrwq_base; /* VBR Wait Queue Base */
ffreg_t abrwq_base; /* ABR Wait Queue Base */
ffreg_t ubrwq_base; /* UBR Wait Queue Base */
ffreg_t vct_base; /* Main VC Table Base */
ffreg_t vcte_base; /* Extended Main VC Table Base */
ffreg_t cbr_tab_beg; /* CBR Table Begin */
ffreg_t cbr_tab_end; /* CBR Table End */
ffreg_t cbr_pointer; /* CBR Pointer */
ffreg_t prq_st_adr; /* Packet Ready Queue Start Address */
ffreg_t prq_ed_adr; /* Packet Ready Queue End Address */
ffreg_t prq_rd_ptr; /* Packet Ready Queue read pointer */
ffreg_t prq_wr_ptr; /* Packet Ready Queue write pointer */
ffreg_t tcq_st_adr; /* Transmit Complete Queue Start Address*/
ffreg_t tcq_ed_adr; /* Transmit Complete Queue End Address */
ffreg_t tcq_rd_ptr; /* Transmit Complete Queue read pointer */
ffreg_t tcq_wr_ptr; /* Transmit Complete Queue write pointer*/
ffreg_t queue_base; /* Base address for PRQ and TCQ */
ffreg_t desc_base; /* Base address of descriptor table */
ffreg_t mode_reg_0; /* Mode register 0 */
ffreg_t mode_reg_1; /* Mode register 1 */
ffreg_t intr_status_reg;/* Interrupt Status register */
ffreg_t mask_reg; /* Mask Register */
ffreg_t cell_ctr_high1; /* Total cell transfer count (high) */
ffreg_t cell_ctr_lo1; /* Total cell transfer count (low) */
ffreg_t state_reg; /* Status register */
ffreg_t curr_desc_num; /* Contains the current descriptor num */
ffreg_t next_desc; /* Next descriptor */
ffreg_t next_vc; /* Next VC */
ffreg_t present_slot_cnt;/* Present slot count */
ffreg_t new_desc_num; /* New descriptor number */
ffreg_t new_vc; /* New VC */
ffreg_t sched_tbl_ptr; /* Schedule table pointer */
ffreg_t vbrwq_wptr; /* VBR wait queue write pointer */
ffreg_t vbrwq_rptr; /* VBR wait queue read pointer */
ffreg_t abrwq_wptr; /* ABR wait queue write pointer */
ffreg_t abrwq_rptr; /* ABR wait queue read pointer */
ffreg_t ubrwq_wptr; /* UBR wait queue write pointer */
ffreg_t ubrwq_rptr; /* UBR wait queue read pointer */
ffreg_t cbr_vc; /* CBR VC */
ffreg_t vbr_sb_vc; /* VBR SB VC */
ffreg_t abr_sb_vc; /* ABR SB VC */
ffreg_t ubr_sb_vc; /* UBR SB VC */
ffreg_t vbr_next_link; /* VBR next link */
ffreg_t abr_next_link; /* ABR next link */
ffreg_t ubr_next_link; /* UBR next link */
ffreg_t out_rate_head; /* Out of rate head */
ffreg_t cell_ctr_high1_nc;/* Total cell transfer count (high) */
ffreg_t cell_ctr_lo1_nc;/* Total cell transfer count (low) */