drivers/gpu/drm/nouveau/include/nvkm/core/falcon.h

132

struct nvkm_falcon *falcon;

drivers/gpu/drm/nouveau/include/nvkm/core/falcon.h

143

struct nvkm_falcon *falcon, struct nvkm_falcon_fw *fw);

drivers/gpu/drm/nouveau/include/nvkm/core/falcon.h

168

#define FLCNFW_PRINTK(f,l,p,fmt,a...) FLCN_PRINTK((f)->falcon, l, p, "%s: "fmt, (f)->fw.name, ##a)

drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h

113

nvkm_falcon_rd32(struct nvkm_falcon *falcon, u32 addr)

drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h

115

return nvkm_rd32(falcon->owner->device, falcon->addr + addr);

drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h

119

nvkm_falcon_wr32(struct nvkm_falcon *falcon, u32 addr, u32 data)

drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h

121

nvkm_wr32(falcon->owner->device, falcon->addr + addr, data);

drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h

125

nvkm_falcon_mask(struct nvkm_falcon *falcon, u32 addr, u32 mask, u32 val)

drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h

127

struct nvkm_device *device = falcon->owner->device;

drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h

129

return nvkm_mask(device, falcon->addr + addr, mask, val);

drivers/gpu/drm/nouveau/include/nvkm/engine/nvdec.h

11

struct nvkm_falcon falcon;

drivers/gpu/drm/nouveau/include/nvkm/engine/nvenc.h

11

struct nvkm_falcon falcon;

drivers/gpu/drm/nouveau/include/nvkm/engine/sec2.h

11

struct nvkm_falcon falcon;

drivers/gpu/drm/nouveau/include/nvkm/subdev/acr.h

74

struct nvkm_falcon *falcon;

drivers/gpu/drm/nouveau/include/nvkm/subdev/fsp.h

14

struct nvkm_falcon falcon;

drivers/gpu/drm/nouveau/include/nvkm/subdev/gsp.h

68

struct nvkm_falcon falcon;

drivers/gpu/drm/nouveau/include/nvkm/subdev/gsp.h

83

} falcon;

drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h

10

struct nvkm_falcon falcon;

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

100

const u32 base = falcon->addr;

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

103

nvkm_memory_unref(&falcon->core);

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

104

if (falcon->external) {

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

105

vfree(falcon->data.data);

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

106

vfree(falcon->code.data);

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

107

falcon->code.data = NULL;

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

131

struct nvkm_falcon *falcon = nvkm_falcon(engine);

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

132

struct nvkm_subdev *subdev = &falcon->engine.subdev;

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

134

const u32 base = falcon->addr;

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

140

falcon->version = 0;

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

141

falcon->secret = (falcon->addr == 0x087000) ? 1 : 0;

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

144

falcon->version = (caps & 0x0000000f);

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

145

falcon->secret = (caps & 0x00000030) >> 4;

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

149

falcon->code.limit = (caps & 0x000001ff) << 8;

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

150

falcon->data.limit = (caps & 0x0003fe00) >> 1;

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

152

nvkm_debug(subdev, "falcon version: %d\n", falcon->version);

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

153

nvkm_debug(subdev, "secret level: %d\n", falcon->secret);

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

154

nvkm_debug(subdev, "code limit: %d\n", falcon->code.limit);

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

155

nvkm_debug(subdev, "data limit: %d\n", falcon->data.limit);

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

162

struct nvkm_falcon *falcon = nvkm_falcon(engine);

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

163

struct nvkm_subdev *subdev = &falcon->engine.subdev;

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

167

const u32 base = falcon->addr;

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

171

if (falcon->secret && falcon->version < 4) {

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

172

if (!falcon->version) {

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

192

if (!falcon->code.data) {

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

194

device->chipset, falcon->addr >> 12);

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

198

falcon->code.data = vmemdup(fw->data, fw->size);

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

199

falcon->code.size = fw->size;

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

200

falcon->data.data = NULL;

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

201

falcon->data.size = 0;

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

205

falcon->external = true;

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

211

if (!falcon->code.data) {

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

213

device->chipset, falcon->addr >> 12);

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

221

falcon->data.data = vmemdup(fw->data, fw->size);

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

222

falcon->data.size = fw->size;

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

224

if (!falcon->data.data)

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

228

device->chipset, falcon->addr >> 12);

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

236

falcon->code.data = vmemdup(fw->data, fw->size);

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

237

falcon->code.size = fw->size;

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

239

if (!falcon->code.data)

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

243

nvkm_debug(subdev, "firmware: %s (%s)\n", name, falcon->data.data ?

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

247

if (!falcon->data.data && !falcon->core) {

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

249

falcon->code.size, 256, false,

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

250

&falcon->core);

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

256

nvkm_kmap(falcon->core);

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

257

for (i = 0; i < falcon->code.size; i += 4)

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

258

nvkm_wo32(falcon->core, i, falcon->code.data[i / 4]);

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

259

nvkm_done(falcon->core);

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

263

if (falcon->core) {

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

264

u64 addr = nvkm_memory_addr(falcon->core);

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

274

if (falcon->code.size > falcon->code.limit ||

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

275

falcon->data.size > falcon->data.limit) {

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

280

if (falcon->version < 3) {

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

282

for (i = 0; i < falcon->code.size / 4; i++)

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

283

nvkm_wr32(device, base + 0xff4, falcon->code.data[i]);

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

286

for (i = 0; i < falcon->code.size / 4; i++) {

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

289

nvkm_wr32(device, base + 0x184, falcon->code.data[i]);

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

295

if (falcon->version < 3) {

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

297

for (i = 0; !falcon->core && i < falcon->data.size / 4; i++)

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

298

nvkm_wr32(device, base + 0xff4, falcon->data.data[i]);

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

299

for (; i < falcon->data.limit; i += 4)

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

303

for (i = 0; !falcon->core && i < falcon->data.size / 4; i++)

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

304

nvkm_wr32(device, base + 0x1c4, falcon->data.data[i]);

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

305

for (; i < falcon->data.limit / 4; i++)

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

315

if (falcon->func->init)

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

316

falcon->func->init(falcon);

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

32

struct nvkm_falcon *falcon = nvkm_falcon(oclass->engine);

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

342

struct nvkm_falcon *falcon;

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

344

if (!(falcon = kzalloc_obj(*falcon)))

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

346

falcon->func = func;

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

347

falcon->addr = addr;

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

348

falcon->code.data = func->code.data;

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

349

falcon->code.size = func->code.size;

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

35

while (falcon->func->sclass[c].oclass) {

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

350

falcon->data.data = func->data.data;

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

351

falcon->data.size = func->data.size;

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

352

*pengine = &falcon->engine;

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

354

return nvkm_engine_ctor(&nvkm_falcon, device, type, inst, enable, &falcon->engine);

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

37

oclass->base = falcon->func->sclass[index];

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

61

struct nvkm_falcon *falcon = nvkm_falcon(engine);

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

62

struct nvkm_subdev *subdev = &falcon->engine.subdev;

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

64

const u32 base = falcon->addr;

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

74

if (falcon->func->intr) {

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

75

falcon->func->intr(falcon, chan);

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

98

struct nvkm_falcon *falcon = nvkm_falcon(engine);

drivers/gpu/drm/nouveau/nvkm/engine/falcon.c

99

struct nvkm_device *device = falcon->engine.subdev.device;

drivers/gpu/drm/nouveau/nvkm/engine/gr/ga102.c

320

ret = nvkm_acr_lsfw_load_bl_sig_net(subdev, &gr->fecs.falcon, NVKM_ACR_LSF_FECS,

drivers/gpu/drm/nouveau/nvkm/engine/gr/ga102.c

329

ret = nvkm_acr_lsfw_load_bl_sig_net(subdev, &gr->gpccs.falcon, NVKM_ACR_LSF_GPCCS,

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

1700

gf100_gr_init_fw(struct nvkm_falcon *falcon,

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

1703

nvkm_falcon_load_dmem(falcon, data->data, 0x0, data->size, 0);

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

1704

nvkm_falcon_load_imem(falcon, code->data, 0x0, code->size, 0, 0, false);

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

1710

u32 falcon, u32 starstar, u32 base)

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

1718

nvkm_wr32(device, falcon + 0x01c0, 0x02000000 + starstar);

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

1719

star = nvkm_rd32(device, falcon + 0x01c4);

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

1720

temp = nvkm_rd32(device, falcon + 0x01c4);

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

1723

nvkm_wr32(device, falcon + 0x01c0, 0x01000000 + star);

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

1732

nvkm_wr32(device, falcon + 0x01c4, data);

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

1744

nvkm_wr32(device, falcon + 0x01c4, (--xfer << 26) | addr);

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

1745

nvkm_wr32(device, falcon + 0x01c0, 0x01000004 + starstar);

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

1746

nvkm_wr32(device, falcon + 0x01c4, star + 4);

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

1764

gf100_gr_init_fw(&gr->fecs.falcon, &gr->fecs.inst,

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

1771

gf100_gr_init_fw(&gr->gpccs.falcon, &gr->gpccs.inst,

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

1790

nvkm_falcon_start(&gr->gpccs.falcon);

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

1791

nvkm_falcon_start(&gr->fecs.falcon);

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

1844

nvkm_falcon_load_dmem(&gr->fecs.falcon,

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

1847

nvkm_falcon_load_imem(&gr->fecs.falcon,

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

1852

nvkm_falcon_load_dmem(&gr->gpccs.falcon,

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

1855

nvkm_falcon_load_imem(&gr->gpccs.falcon,

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

2099

ret = nvkm_falcon_get(&gr->fecs.falcon, subdev);

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

2103

ret = nvkm_falcon_get(&gr->gpccs.falcon, subdev);

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

2123

nvkm_falcon_put(&gr->gpccs.falcon, subdev);

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

2124

nvkm_falcon_put(&gr->fecs.falcon, subdev);

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

2140

nvkm_falcon_dtor(&gr->gpccs.falcon);

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

2141

nvkm_falcon_dtor(&gr->fecs.falcon);

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

2642

"fecs", 0x409000, &gr->fecs.falcon);

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

2649

"gpccs", 0x41a000, &gr->gpccs.falcon);

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h

70

struct nvkm_falcon falcon;

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h

79

struct nvkm_falcon falcon;

drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c

227

&gr->fecs.falcon,

drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c

234

&gr->gpccs.falcon,

drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c

146

ret = nvkm_acr_lsfw_load_bl_inst_data_sig(subdev, &gr->fecs.falcon,

drivers/gpu/drm/nouveau/nvkm/engine/nvdec/base.c

29

nvkm_falcon_dtor(&nvdec->falcon);

drivers/gpu/drm/nouveau/nvkm/engine/nvdec/base.c

61

nvdec->engine.subdev.name, addr, &nvdec->falcon);

drivers/gpu/drm/nouveau/nvkm/engine/nvenc/base.c

30

nvkm_falcon_dtor(&nvenc->falcon);

drivers/gpu/drm/nouveau/nvkm/engine/nvenc/base.c

62

nvenc->engine.subdev.name, 0, &nvenc->falcon);

drivers/gpu/drm/nouveau/nvkm/engine/sec2/base.c

121

nvkm_falcon_dtor(&sec2->falcon);

drivers/gpu/drm/nouveau/nvkm/engine/sec2/base.c

154

sec2->engine.subdev.name, addr, &sec2->falcon);

drivers/gpu/drm/nouveau/nvkm/engine/sec2/base.c

158

if ((ret = nvkm_falcon_qmgr_new(&sec2->falcon, &sec2->qmgr)) ||

drivers/gpu/drm/nouveau/nvkm/engine/sec2/base.c

44

struct nvkm_falcon *falcon = &sec2->falcon;

drivers/gpu/drm/nouveau/nvkm/engine/sec2/base.c

61

if (nvkm_falcon_rd32(falcon, 0x100) & 0x00000010)

drivers/gpu/drm/nouveau/nvkm/engine/sec2/base.c

69

falcon->func->disable(falcon);

drivers/gpu/drm/nouveau/nvkm/engine/sec2/base.c

70

nvkm_falcon_put(falcon, subdev);

drivers/gpu/drm/nouveau/nvkm/engine/sec2/base.c

79

struct nvkm_falcon *falcon = &sec2->falcon;

drivers/gpu/drm/nouveau/nvkm/engine/sec2/base.c

82

ret = nvkm_falcon_get(falcon, subdev);

drivers/gpu/drm/nouveau/nvkm/engine/sec2/base.c

86

nvkm_falcon_wr32(falcon, 0x014, 0xffffffff);

drivers/gpu/drm/nouveau/nvkm/engine/sec2/base.c

91

nvkm_falcon_start(falcon);

drivers/gpu/drm/nouveau/nvkm/engine/sec2/ga102.c

180

return nvkm_acr_lsfw_load_sig_image_desc_v2(&sec2->engine.subdev, &sec2->falcon,

drivers/gpu/drm/nouveau/nvkm/engine/sec2/ga102.c

63

struct nvkm_falcon *falcon = &sec2->falcon;

drivers/gpu/drm/nouveau/nvkm/engine/sec2/ga102.c

66

ret = ga102_flcn_select(falcon);

drivers/gpu/drm/nouveau/nvkm/engine/sec2/ga102.c

93

ga102_sec2_acr_bootstrap_falcon(struct nvkm_falcon *falcon, enum nvkm_acr_lsf_id id)

drivers/gpu/drm/nouveau/nvkm/engine/sec2/ga102.c

95

struct nvkm_sec2 *sec2 = container_of(falcon, typeof(*sec2), falcon);

drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c

104

.argv = lsfw->falcon->func->emem_addr,

drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c

157

struct nvkm_falcon *falcon = &sec2->falcon;

drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c

158

u32 disp = nvkm_falcon_rd32(falcon, 0x01c);

drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c

159

u32 intr = nvkm_falcon_rd32(falcon, 0x008) & disp & ~(disp >> 16);

drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c

176

nvkm_falcon_wr32(falcon, 0x004, 0x00000040);

drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c

182

FLCN_ERR(falcon, "halted");

drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c

183

gm200_flcn_tracepc(falcon);

drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c

186

nvkm_falcon_wr32(falcon, 0x004, 0x00000010);

drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c

192

nvkm_falcon_wr32(falcon, 0x004, intr);

drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c

265

.argv = lsfw->falcon->func->emem_addr,

drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c

287

&sec2->falcon,

drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c

59

gp102_sec2_acr_bootstrap_falcon(struct nvkm_falcon *falcon,

drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c

62

struct nvkm_sec2 *sec2 = container_of(falcon, typeof(*sec2), falcon);

drivers/gpu/drm/nouveau/nvkm/engine/sec2/r535.c

29

nvkm_falcon_dtor(&sec2->falcon);

drivers/gpu/drm/nouveau/nvkm/engine/sec2/r535.c

53

addr, &sec2->falcon);

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

104

if (nvkm_msec(falcon->owner->device, 2000,

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

105

if (dma->done(falcon))

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

121

nvkm_falcon_pio(struct nvkm_falcon *falcon, enum nvkm_falcon_mem *mem_type, u32 *mem_base)

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

125

return falcon->func->imem_pio;

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

127

if (!falcon->func->emem_addr || *mem_base < falcon->func->emem_addr)

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

128

return falcon->func->dmem_pio;

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

130

*mem_base -= falcon->func->emem_addr;

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

133

return falcon->func->emem_pio;

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

140

nvkm_falcon_pio_rd(struct nvkm_falcon *falcon, u8 port, enum nvkm_falcon_mem mem_type, u32 mem_base,

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

143

const struct nvkm_falcon_func_pio *pio = nvkm_falcon_pio(falcon, &mem_type, &mem_base);

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

150

FLCN_DBG(falcon, "%s %08x -> %08x bytes at %08x", type, mem_base, len, img_base);

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

154

pio->rd_init(falcon, port, mem_base);

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

157

pio->rd(falcon, port, img, xfer_len);

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

159

if (nvkm_printk_ok(falcon->owner, falcon->user, NV_DBG_TRACE)) {

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

175

nvkm_falcon_pio_wr(struct nvkm_falcon *falcon, const u8 *img, u32 img_base, u8 port,

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

178

const struct nvkm_falcon_func_pio *pio = nvkm_falcon_pio(falcon, &mem_type, &mem_base);

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

185

FLCN_DBG(falcon, "%s %08x <- %08x bytes at %08x", type, mem_base, len, img_base);

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

189

pio->wr_init(falcon, port, sec, mem_base);

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

192

pio->wr(falcon, port, img, xfer_len, tag++);

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

194

if (nvkm_printk_ok(falcon->owner, falcon->user, NV_DBG_TRACE)) {

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

212

nvkm_falcon_load_imem(struct nvkm_falcon *falcon, void *data, u32 start,

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

215

if (secure && !falcon->secret) {

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

216

nvkm_warn(falcon->user,

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

221

falcon->func->load_imem(falcon, data, start, size, tag, port,

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

226

nvkm_falcon_load_dmem(struct nvkm_falcon *falcon, void *data, u32 start,

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

229

mutex_lock(&falcon->dmem_mutex);

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

231

falcon->func->load_dmem(falcon, data, start, size, port);

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

233

mutex_unlock(&falcon->dmem_mutex);

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

237

nvkm_falcon_start(struct nvkm_falcon *falcon)

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

239

falcon->func->start(falcon);

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

243

nvkm_falcon_reset(struct nvkm_falcon *falcon)

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

247

ret = falcon->func->disable(falcon);

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

251

return nvkm_falcon_enable(falcon);

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

255

nvkm_falcon_oneinit(struct nvkm_falcon *falcon)

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

257

const struct nvkm_falcon_func *func = falcon->func;

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

258

const struct nvkm_subdev *subdev = falcon->owner;

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

261

if (!falcon->addr) {

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

262

falcon->addr = nvkm_top_addr(subdev->device, subdev->type, subdev->inst);

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

263

if (WARN_ON(!falcon->addr))

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

267

reg = nvkm_falcon_rd32(falcon, 0x12c);

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

268

falcon->version = reg & 0xf;

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

269

falcon->secret = (reg >> 4) & 0x3;

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

270

falcon->code.ports = (reg >> 8) & 0xf;

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

271

falcon->data.ports = (reg >> 12) & 0xf;

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

273

reg = nvkm_falcon_rd32(falcon, 0x108);

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

274

falcon->code.limit = (reg & 0x1ff) << 8;

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

275

falcon->data.limit = (reg & 0x3fe00) >> 1;

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

278

u32 val = nvkm_falcon_rd32(falcon, func->debug);

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

279

falcon->debug = (val >> 20) & 0x1;

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

286

nvkm_falcon_put(struct nvkm_falcon *falcon, struct nvkm_subdev *user)

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

288

if (unlikely(!falcon))

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

29

nvkm_falcon_intr_retrigger(struct nvkm_falcon *falcon)

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

291

mutex_lock(&falcon->mutex);

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

292

if (falcon->user == user) {

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

293

nvkm_debug(falcon->user, "released %s falcon\n", falcon->name);

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

294

falcon->user = NULL;

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

296

mutex_unlock(&falcon->mutex);

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

300

nvkm_falcon_get(struct nvkm_falcon *falcon, struct nvkm_subdev *user)

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

304

mutex_lock(&falcon->mutex);

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

305

if (falcon->user) {

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

307

falcon->name, falcon->user->name);

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

308

mutex_unlock(&falcon->mutex);

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

31

if (falcon->func->intr_retrigger)

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

312

nvkm_debug(user, "acquired %s falcon\n", falcon->name);

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

313

if (!falcon->oneinit)

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

314

ret = nvkm_falcon_oneinit(falcon);

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

315

falcon->user = user;

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

316

mutex_unlock(&falcon->mutex);

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

32

falcon->func->intr_retrigger(falcon);

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

321

nvkm_falcon_dtor(struct nvkm_falcon *falcon)

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

328

struct nvkm_falcon *falcon)

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

330

falcon->func = func;

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

331

falcon->owner = subdev;

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

332

falcon->name = name;

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

333

falcon->addr = addr;

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

334

falcon->addr2 = func->addr2;

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

335

mutex_init(&falcon->mutex);

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

336

mutex_init(&falcon->dmem_mutex);

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

36

nvkm_falcon_riscv_active(struct nvkm_falcon *falcon)

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

38

if (!falcon->func->riscv_active)

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

41

return falcon->func->riscv_active(falcon);

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

45

nvkm_falcon_dma(struct nvkm_falcon *falcon, enum nvkm_falcon_mem *mem_type, u32 *mem_base)

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

48

case IMEM: return falcon->func->imem_dma;

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

49

case DMEM: return falcon->func->dmem_dma;

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

56

nvkm_falcon_dma_wr(struct nvkm_falcon *falcon, const u8 *img, u64 dma_addr, u32 dma_base,

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

59

const struct nvkm_falcon_func_dma *dma = nvkm_falcon_dma(falcon, &mem_type, &mem_base);

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

74

FLCN_DBG(falcon, "%s %08x <- %08x bytes at %08x (%010llx %08x)",

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

79

ret = dma->init(falcon, dma_addr, dmalen, mem_type, sec, &cmd);

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

87

dma->xfer(falcon, dst, src - dma_start, cmd);

drivers/gpu/drm/nouveau/nvkm/falcon/base.c

89

if (img && nvkm_printk_ok(falcon->owner, falcon->user, NV_DBG_TRACE)) {

drivers/gpu/drm/nouveau/nvkm/falcon/cmdq.c

178

const struct nvkm_falcon_func *func = cmdq->qmgr->falcon->func;

drivers/gpu/drm/nouveau/nvkm/falcon/cmdq.c

28

u32 head = nvkm_falcon_rd32(cmdq->qmgr->falcon, cmdq->head_reg);

drivers/gpu/drm/nouveau/nvkm/falcon/cmdq.c

29

u32 tail = nvkm_falcon_rd32(cmdq->qmgr->falcon, cmdq->tail_reg);

drivers/gpu/drm/nouveau/nvkm/falcon/cmdq.c

53

struct nvkm_falcon *falcon = cmdq->qmgr->falcon;

drivers/gpu/drm/nouveau/nvkm/falcon/cmdq.c

54

nvkm_falcon_pio_wr(falcon, data, 0, 0, DMEM, cmdq->position, size, 0, false);

drivers/gpu/drm/nouveau/nvkm/falcon/cmdq.c

73

struct nvkm_falcon *falcon = cmdq->qmgr->falcon;

drivers/gpu/drm/nouveau/nvkm/falcon/cmdq.c

84

cmdq->position = nvkm_falcon_rd32(falcon, cmdq->head_reg);

drivers/gpu/drm/nouveau/nvkm/falcon/cmdq.c

95

nvkm_falcon_wr32(cmdq->qmgr->falcon, cmdq->head_reg, cmdq->position);

drivers/gpu/drm/nouveau/nvkm/falcon/fw.c

122

nvkm_falcon_put(falcon, user);

drivers/gpu/drm/nouveau/nvkm/falcon/fw.c

127

nvkm_falcon_fw_oneinit(struct nvkm_falcon_fw *fw, struct nvkm_falcon *falcon,

drivers/gpu/drm/nouveau/nvkm/falcon/fw.c

132

fw->falcon = falcon;

drivers/gpu/drm/nouveau/nvkm/falcon/fw.c

137

FLCN_DBG(falcon, "mapping %s fw", fw->fw.name);

drivers/gpu/drm/nouveau/nvkm/falcon/fw.c

140

FLCN_ERR(falcon, "get %d", ret);

drivers/gpu/drm/nouveau/nvkm/falcon/fw.c

146

FLCN_ERR(falcon, "map %d", ret);

drivers/gpu/drm/nouveau/nvkm/falcon/fw.c

200

struct nvkm_falcon *falcon, struct nvkm_falcon_fw *fw)

drivers/gpu/drm/nouveau/nvkm/falcon/fw.c

211

return falcon ? nvkm_falcon_fw_oneinit(fw, falcon, NULL, NULL) : 0;

drivers/gpu/drm/nouveau/nvkm/falcon/fw.c

217

struct nvkm_falcon *falcon, struct nvkm_falcon_fw *fw)

drivers/gpu/drm/nouveau/nvkm/falcon/fw.c

235

blob->data + hdr->data_offset, hdr->data_size, falcon, fw);

drivers/gpu/drm/nouveau/nvkm/falcon/fw.c

310

struct nvkm_falcon *falcon, struct nvkm_falcon_fw *fw)

drivers/gpu/drm/nouveau/nvkm/falcon/fw.c

33

struct nvkm_falcon *falcon = fw->falcon;

drivers/gpu/drm/nouveau/nvkm/falcon/fw.c

331

blob->data + hdr->data_offset, hdr->data_size, falcon, fw);

drivers/gpu/drm/nouveau/nvkm/falcon/fw.c

52

if (nvkm_printk_ok(falcon->owner, falcon->user, NV_DBG_TRACE)) {

drivers/gpu/drm/nouveau/nvkm/falcon/fw.c

77

struct nvkm_falcon *falcon = fw->falcon;

drivers/gpu/drm/nouveau/nvkm/falcon/fw.c

80

ret = nvkm_falcon_get(falcon, user);

drivers/gpu/drm/nouveau/nvkm/falcon/ga100.c

25

ga100_flcn_intr_retrigger(struct nvkm_falcon *falcon)

drivers/gpu/drm/nouveau/nvkm/falcon/ga100.c

27

nvkm_falcon_wr32(falcon, 0x3e8, 0x00000001);

drivers/gpu/drm/nouveau/nvkm/falcon/ga100.c

33

struct nvkm_falcon *falcon = fw->falcon;

drivers/gpu/drm/nouveau/nvkm/falcon/ga100.c

34

struct nvkm_device *device = falcon->owner->device;

drivers/gpu/drm/nouveau/nvkm/falcon/ga100.c

38

FLCN_DBG(falcon, "brom: %08x %08x", fw->engine_id, fw->ucode_id);

drivers/gpu/drm/nouveau/nvkm/falcon/ga100.c

39

FLCN_DBG(falcon, "fuse_version: %d", fw->fuse_ver);

drivers/gpu/drm/nouveau/nvkm/falcon/ga100.c

54

FLCN_DBG(falcon, "reg_fuse_version: %08x", reg_fuse_version);

drivers/gpu/drm/nouveau/nvkm/falcon/ga100.c

57

FLCN_DBG(falcon, "reg_fuse_version: %d", reg_fuse_version);

drivers/gpu/drm/nouveau/nvkm/falcon/ga102.c

100

if ((nvkm_falcon_rd32(falcon, falcon->addr2 + 0x668) & 0x00000010) != 0x00000000) {

drivers/gpu/drm/nouveau/nvkm/falcon/ga102.c

101

nvkm_falcon_wr32(falcon, falcon->addr2 + 0x668, 0x00000000);

drivers/gpu/drm/nouveau/nvkm/falcon/ga102.c

102

if (nvkm_msec(falcon->owner->device, 10,

drivers/gpu/drm/nouveau/nvkm/falcon/ga102.c

103

if (nvkm_falcon_rd32(falcon, falcon->addr2 + 0x668) & 0x00000001)

drivers/gpu/drm/nouveau/nvkm/falcon/ga102.c

115

struct nvkm_falcon *falcon = fw->falcon;

drivers/gpu/drm/nouveau/nvkm/falcon/ga102.c

117

nvkm_falcon_wr32(falcon, falcon->addr2 + 0x210, fw->dmem_sign);

drivers/gpu/drm/nouveau/nvkm/falcon/ga102.c

118

nvkm_falcon_wr32(falcon, falcon->addr2 + 0x19c, fw->engine_id);

drivers/gpu/drm/nouveau/nvkm/falcon/ga102.c

119

nvkm_falcon_wr32(falcon, falcon->addr2 + 0x198, fw->ucode_id);

drivers/gpu/drm/nouveau/nvkm/falcon/ga102.c

120

nvkm_falcon_wr32(falcon, falcon->addr2 + 0x180, 0x00000001);

drivers/gpu/drm/nouveau/nvkm/falcon/ga102.c

128

struct nvkm_falcon *falcon = fw->falcon;

drivers/gpu/drm/nouveau/nvkm/falcon/ga102.c

131

nvkm_falcon_mask(falcon, 0x624, 0x00000080, 0x00000080);

drivers/gpu/drm/nouveau/nvkm/falcon/ga102.c

132

nvkm_falcon_wr32(falcon, 0x10c, 0x00000000);

drivers/gpu/drm/nouveau/nvkm/falcon/ga102.c

133

nvkm_falcon_mask(falcon, 0x600, 0x00010007, (0 << 16) | (1 << 2) | 1);

drivers/gpu/drm/nouveau/nvkm/falcon/ga102.c

135

ret = nvkm_falcon_dma_wr(falcon, fw->fw.img, fw->fw.phys, fw->imem_base_img,

drivers/gpu/drm/nouveau/nvkm/falcon/ga102.c

140

ret = nvkm_falcon_dma_wr(falcon, fw->fw.img, fw->fw.phys, fw->dmem_base_img,

drivers/gpu/drm/nouveau/nvkm/falcon/ga102.c

28

ga102_flcn_riscv_active(struct nvkm_falcon *falcon)

drivers/gpu/drm/nouveau/nvkm/falcon/ga102.c

30

return (nvkm_falcon_rd32(falcon, falcon->addr2 + 0x388) & 0x00000080) != 0;

drivers/gpu/drm/nouveau/nvkm/falcon/ga102.c

34

ga102_flcn_dma_done(struct nvkm_falcon *falcon)

drivers/gpu/drm/nouveau/nvkm/falcon/ga102.c

36

return !!(nvkm_falcon_rd32(falcon, 0x118) & 0x00000002);

drivers/gpu/drm/nouveau/nvkm/falcon/ga102.c

40

ga102_flcn_dma_xfer(struct nvkm_falcon *falcon, u32 mem_base, u32 dma_base, u32 cmd)

drivers/gpu/drm/nouveau/nvkm/falcon/ga102.c

42

nvkm_falcon_wr32(falcon, 0x114, mem_base);

drivers/gpu/drm/nouveau/nvkm/falcon/ga102.c

43

nvkm_falcon_wr32(falcon, 0x11c, dma_base);

drivers/gpu/drm/nouveau/nvkm/falcon/ga102.c

44

nvkm_falcon_wr32(falcon, 0x118, cmd);

drivers/gpu/drm/nouveau/nvkm/falcon/ga102.c

48

ga102_flcn_dma_init(struct nvkm_falcon *falcon, u64 dma_addr, int xfer_len,

drivers/gpu/drm/nouveau/nvkm/falcon/ga102.c

57

nvkm_falcon_wr32(falcon, 0x110, dma_addr >> 8);

drivers/gpu/drm/nouveau/nvkm/falcon/ga102.c

58

nvkm_falcon_wr32(falcon, 0x128, 0x00000000);

drivers/gpu/drm/nouveau/nvkm/falcon/ga102.c

70

ga102_flcn_reset_wait_mem_scrubbing(struct nvkm_falcon *falcon)

drivers/gpu/drm/nouveau/nvkm/falcon/ga102.c

72

nvkm_falcon_mask(falcon, 0x040, 0x00000000, 0x00000000);

drivers/gpu/drm/nouveau/nvkm/falcon/ga102.c

74

if (nvkm_msec(falcon->owner->device, 20,

drivers/gpu/drm/nouveau/nvkm/falcon/ga102.c

75

if (!(nvkm_falcon_rd32(falcon, 0x0f4) & 0x00001000))

drivers/gpu/drm/nouveau/nvkm/falcon/ga102.c

84

ga102_flcn_reset_prep(struct nvkm_falcon *falcon)

drivers/gpu/drm/nouveau/nvkm/falcon/ga102.c

86

nvkm_falcon_rd32(falcon, 0x0f4);

drivers/gpu/drm/nouveau/nvkm/falcon/ga102.c

88

nvkm_usec(falcon->owner->device, 150,

drivers/gpu/drm/nouveau/nvkm/falcon/ga102.c

89

if (nvkm_falcon_rd32(falcon, 0x0f4) & 0x80000000)

drivers/gpu/drm/nouveau/nvkm/falcon/ga102.c

98

ga102_flcn_select(struct nvkm_falcon *falcon)

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

100

nvkm_falcon_wr32(falcon, 0x180 + (port * 0x10), (sec ? BIT(28) : 0) | BIT(24) | imem_base);

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

104

gm200_flcn_pio_imem_wr(struct nvkm_falcon *falcon, u8 port, const u8 *img, int len, u16 tag)

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

106

nvkm_falcon_wr32(falcon, 0x188 + (port * 0x10), tag);

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

108

nvkm_falcon_wr32(falcon, 0x184 + (port * 0x10), *(u32 *)img);

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

123

gm200_flcn_bind_stat(struct nvkm_falcon *falcon, bool intr)

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

125

if (intr && !(nvkm_falcon_rd32(falcon, 0x008) & 0x00000008))

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

128

return (nvkm_falcon_rd32(falcon, 0x0dc) & 0x00007000) >> 12;

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

132

gm200_flcn_bind_inst(struct nvkm_falcon *falcon, int target, u64 addr)

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

134

nvkm_falcon_mask(falcon, 0x604, 0x00000007, 0x00000000); /* DMAIDX_VIRT */

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

135

nvkm_falcon_wr32(falcon, 0x054, (1 << 30) | (target << 28) | (addr >> 12));

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

136

nvkm_falcon_mask(falcon, 0x090, 0x00010000, 0x00010000);

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

137

nvkm_falcon_mask(falcon, 0x0a4, 0x00000008, 0x00000008);

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

141

gm200_flcn_reset_wait_mem_scrubbing(struct nvkm_falcon *falcon)

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

143

nvkm_falcon_mask(falcon, 0x040, 0x00000000, 0x00000000);

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

145

if (nvkm_msec(falcon->owner->device, 10,

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

146

if (!(nvkm_falcon_rd32(falcon, 0x10c) & 0x00000006))

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

155

gm200_flcn_enable(struct nvkm_falcon *falcon)

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

157

struct nvkm_device *device = falcon->owner->device;

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

160

if (falcon->func->reset_eng) {

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

161

ret = falcon->func->reset_eng(falcon);

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

166

if (falcon->func->select) {

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

167

ret = falcon->func->select(falcon);

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

172

if (falcon->func->reset_pmc)

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

173

nvkm_mc_enable(device, falcon->owner->type, falcon->owner->inst);

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

175

ret = falcon->func->reset_wait_mem_scrubbing(falcon);

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

179

nvkm_falcon_wr32(falcon, 0x084, nvkm_rd32(device, 0x000000));

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

184

gm200_flcn_disable(struct nvkm_falcon *falcon)

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

186

struct nvkm_device *device = falcon->owner->device;

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

189

if (falcon->func->select) {

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

190

ret = falcon->func->select(falcon);

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

195

nvkm_falcon_mask(falcon, 0x048, 0x00000003, 0x00000000);

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

196

nvkm_falcon_wr32(falcon, 0x014, 0xffffffff);

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

198

if (falcon->func->reset_pmc) {

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

199

if (falcon->func->reset_prep) {

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

200

ret = falcon->func->reset_prep(falcon);

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

205

nvkm_mc_disable(device, falcon->owner->type, falcon->owner->inst);

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

208

if (falcon->func->reset_eng) {

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

209

ret = falcon->func->reset_eng(falcon);

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

220

struct nvkm_falcon *falcon = fw->falcon;

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

224

nvkm_falcon_wr32(falcon, 0x040, pmbox0 ? *pmbox0 : 0xcafebeef);

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

226

nvkm_falcon_wr32(falcon, 0x044, *pmbox1);

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

228

nvkm_falcon_wr32(falcon, 0x104, fw->boot_addr);

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

229

nvkm_falcon_wr32(falcon, 0x100, 0x00000002);

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

231

if (nvkm_msec(falcon->owner->device, 2000,

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

232

if (nvkm_falcon_rd32(falcon, 0x100) & 0x00000010)

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

237

mbox0 = nvkm_falcon_rd32(falcon, 0x040);

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

238

mbox1 = nvkm_falcon_rd32(falcon, 0x044);

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

239

if (FLCN_ERRON(falcon, ret || mbox0 != mbox0_ok, "mbox %08x %08x", mbox0, mbox1))

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

243

nvkm_falcon_mask(falcon, 0x004, 0xffffffff, irqsclr);

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

251

struct nvkm_falcon *falcon = fw->falcon;

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

257

nvkm_falcon_mask(falcon, 0x048, 0x00000001, 0x00000001);

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

268

falcon->func->bind_inst(falcon, target, nvkm_memory_addr(fw->inst));

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

270

if (nvkm_msec(falcon->owner->device, 10,

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

271

if (falcon->func->bind_stat(falcon, falcon->func->bind_intr) == 5)

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

276

nvkm_falcon_mask(falcon, 0x004, 0x00000008, 0x00000008);

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

277

nvkm_falcon_mask(falcon, 0x058, 0x00000002, 0x00000002);

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

279

if (nvkm_msec(falcon->owner->device, 10,

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

280

if (falcon->func->bind_stat(falcon, false) == 0)

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

285

nvkm_falcon_mask(falcon, 0x624, 0x00000080, 0x00000080);

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

286

nvkm_falcon_wr32(falcon, 0x10c, 0x00000000);

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

29

gm200_flcn_tracepc(struct nvkm_falcon *falcon)

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

290

ret = nvkm_falcon_pio_wr(falcon, fw->boot, 0, 0,

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

291

IMEM, falcon->code.limit - fw->boot_size, fw->boot_size,

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

299

ret = nvkm_falcon_pio_wr(falcon, fw->fw.img + fw->nmem_base_img, fw->nmem_base_img, 0,

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

304

ret = nvkm_falcon_pio_wr(falcon, fw->fw.img + fw->imem_base_img, fw->imem_base_img, 0,

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

309

ret = nvkm_falcon_pio_wr(falcon, fw->fw.img + fw->dmem_base_img, fw->dmem_base_img, 0,

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

31

u32 sctl = nvkm_falcon_rd32(falcon, 0x240);

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

32

u32 tidx = nvkm_falcon_rd32(falcon, 0x148);

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

320

return nvkm_falcon_reset(fw->falcon);

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

326

struct nvkm_falcon *falcon = fw->falcon;

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

327

u32 addr = falcon->func->debug;

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

331

ret = nvkm_falcon_enable(falcon);

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

335

if (nvkm_falcon_rd32(falcon, addr) & 0x00100000) {

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

35

FLCN_ERR(falcon, "TRACEPC SCTL %08x TIDX %08x", sctl, tidx);

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

37

nvkm_falcon_wr32(falcon, 0x148, sp);

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

38

ip = nvkm_falcon_rd32(falcon, 0x14c);

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

39

FLCN_ERR(falcon, "TRACEPC: %08x", ip);

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

44

gm200_flcn_pio_dmem_rd(struct nvkm_falcon *falcon, u8 port, const u8 *img, int len)

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

47

*(u32 *)img = nvkm_falcon_rd32(falcon, 0x1c4 + (port * 8));

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

54

u32 data = nvkm_falcon_rd32(falcon, 0x1c4 + (port * 8));

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

64

gm200_flcn_pio_dmem_rd_init(struct nvkm_falcon *falcon, u8 port, u32 dmem_base)

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

66

nvkm_falcon_wr32(falcon, 0x1c0 + (port * 8), BIT(25) | dmem_base);

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

70

gm200_flcn_pio_dmem_wr(struct nvkm_falcon *falcon, u8 port, const u8 *img, int len, u16 tag)

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

73

nvkm_falcon_wr32(falcon, 0x1c4 + (port * 8), *(u32 *)img);

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

82

gm200_flcn_pio_dmem_wr_init(struct nvkm_falcon *falcon, u8 port, bool sec, u32 dmem_base)

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

84

nvkm_falcon_wr32(falcon, 0x1c0 + (port * 8), BIT(24) | dmem_base);

drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c

98

gm200_flcn_pio_imem_wr_init(struct nvkm_falcon *falcon, u8 port, bool sec, u32 imem_base)

drivers/gpu/drm/nouveau/nvkm/falcon/gp102.c

25

gp102_flcn_pio_emem_rd(struct nvkm_falcon *falcon, u8 port, const u8 *img, int len)

drivers/gpu/drm/nouveau/nvkm/falcon/gp102.c

28

*(u32 *)img = nvkm_falcon_rd32(falcon, 0xac4 + (port * 8));

drivers/gpu/drm/nouveau/nvkm/falcon/gp102.c

35

gp102_flcn_pio_emem_rd_init(struct nvkm_falcon *falcon, u8 port, u32 dmem_base)

drivers/gpu/drm/nouveau/nvkm/falcon/gp102.c

37

nvkm_falcon_wr32(falcon, 0xac0 + (port * 8), BIT(25) | dmem_base);

drivers/gpu/drm/nouveau/nvkm/falcon/gp102.c

41

gp102_flcn_pio_emem_wr(struct nvkm_falcon *falcon, u8 port, const u8 *img, int len, u16 tag)

drivers/gpu/drm/nouveau/nvkm/falcon/gp102.c

44

nvkm_falcon_wr32(falcon, 0xac4 + (port * 8), *(u32 *)img);

drivers/gpu/drm/nouveau/nvkm/falcon/gp102.c

51

gp102_flcn_pio_emem_wr_init(struct nvkm_falcon *falcon, u8 port, bool sec, u32 emem_base)

drivers/gpu/drm/nouveau/nvkm/falcon/gp102.c

53

nvkm_falcon_wr32(falcon, 0xac0 + (port * 8), BIT(24) | emem_base);

drivers/gpu/drm/nouveau/nvkm/falcon/gp102.c

67

gp102_flcn_reset_eng(struct nvkm_falcon *falcon)

drivers/gpu/drm/nouveau/nvkm/falcon/gp102.c

71

if (falcon->func->reset_prep) {

drivers/gpu/drm/nouveau/nvkm/falcon/gp102.c

72

ret = falcon->func->reset_prep(falcon);

drivers/gpu/drm/nouveau/nvkm/falcon/gp102.c

77

nvkm_falcon_mask(falcon, 0x3c0, 0x00000001, 0x00000001);

drivers/gpu/drm/nouveau/nvkm/falcon/gp102.c

79

nvkm_falcon_mask(falcon, 0x3c0, 0x00000001, 0x00000000);

drivers/gpu/drm/nouveau/nvkm/falcon/gp102.c

81

return falcon->func->reset_wait_mem_scrubbing(falcon);

drivers/gpu/drm/nouveau/nvkm/falcon/msgq.c

157

struct nvkm_falcon *falcon = msgq->qmgr->falcon;

drivers/gpu/drm/nouveau/nvkm/falcon/msgq.c

161

msgq->head_reg = falcon->func->msgq.head;

drivers/gpu/drm/nouveau/nvkm/falcon/msgq.c

162

msgq->tail_reg = falcon->func->msgq.tail;

drivers/gpu/drm/nouveau/nvkm/falcon/msgq.c

163

msgq->offset = nvkm_falcon_rd32(falcon, falcon->func->msgq.tail);

drivers/gpu/drm/nouveau/nvkm/falcon/msgq.c

168

FLCN_ERR(falcon, "unexpected init message size %d vs %d",

drivers/gpu/drm/nouveau/nvkm/falcon/msgq.c

180

const struct nvkm_falcon_func *func = msgq->qmgr->falcon->func;

drivers/gpu/drm/nouveau/nvkm/falcon/msgq.c

29

msgq->position = nvkm_falcon_rd32(msgq->qmgr->falcon, msgq->tail_reg);

drivers/gpu/drm/nouveau/nvkm/falcon/msgq.c

35

struct nvkm_falcon *falcon = msgq->qmgr->falcon;

drivers/gpu/drm/nouveau/nvkm/falcon/msgq.c

38

nvkm_falcon_wr32(falcon, msgq->tail_reg, msgq->position);

drivers/gpu/drm/nouveau/nvkm/falcon/msgq.c

46

u32 head = nvkm_falcon_rd32(msgq->qmgr->falcon, msgq->head_reg);

drivers/gpu/drm/nouveau/nvkm/falcon/msgq.c

47

u32 tail = nvkm_falcon_rd32(msgq->qmgr->falcon, msgq->tail_reg);

drivers/gpu/drm/nouveau/nvkm/falcon/msgq.c

54

struct nvkm_falcon *falcon = msgq->qmgr->falcon;

drivers/gpu/drm/nouveau/nvkm/falcon/msgq.c

57

head = nvkm_falcon_rd32(falcon, msgq->head_reg);

drivers/gpu/drm/nouveau/nvkm/falcon/msgq.c

71

nvkm_falcon_pio_rd(falcon, 0, DMEM, tail, data, 0, size);

drivers/gpu/drm/nouveau/nvkm/falcon/priv.h

10

return falcon->func->enable(falcon);

drivers/gpu/drm/nouveau/nvkm/falcon/priv.h

7

nvkm_falcon_enable(struct nvkm_falcon *falcon)

drivers/gpu/drm/nouveau/nvkm/falcon/priv.h

9

if (falcon->func->enable)

drivers/gpu/drm/nouveau/nvkm/falcon/qmgr.c

28

const struct nvkm_subdev *subdev = qmgr->falcon->owner;

drivers/gpu/drm/nouveau/nvkm/falcon/qmgr.c

70

nvkm_falcon_qmgr_new(struct nvkm_falcon *falcon,

drivers/gpu/drm/nouveau/nvkm/falcon/qmgr.c

79

qmgr->falcon = falcon;

drivers/gpu/drm/nouveau/nvkm/falcon/qmgr.h

45

struct nvkm_falcon *falcon;

drivers/gpu/drm/nouveau/nvkm/falcon/qmgr.h

85

#define FLCNQ_PRINTK(q,l,p,f,a...) FLCN_PRINTK((q)->qmgr->falcon, l, p, "%s: "f, (q)->name, ##a)

drivers/gpu/drm/nouveau/nvkm/falcon/tu102.c

25

tu102_flcn_riscv_active(struct nvkm_falcon *falcon)

drivers/gpu/drm/nouveau/nvkm/falcon/tu102.c

27

return (nvkm_falcon_rd32(falcon, falcon->addr2 + 0x240) & 0x00000001) != 0;

drivers/gpu/drm/nouveau/nvkm/falcon/v1.c

100

nvkm_falcon_wr32(falcon, 0x100, 0x2);

drivers/gpu/drm/nouveau/nvkm/falcon/v1.c

29

nvkm_falcon_v1_load_imem(struct nvkm_falcon *falcon, void *data, u32 start,

drivers/gpu/drm/nouveau/nvkm/falcon/v1.c

39

nvkm_falcon_wr32(falcon, 0x180 + (port * 16), reg);

drivers/gpu/drm/nouveau/nvkm/falcon/v1.c

43

nvkm_falcon_wr32(falcon, 0x188 + (port * 16), tag++);

drivers/gpu/drm/nouveau/nvkm/falcon/v1.c

44

nvkm_falcon_wr32(falcon, 0x184 + (port * 16), ((u32 *)data)[i]);

drivers/gpu/drm/nouveau/nvkm/falcon/v1.c

56

nvkm_falcon_wr32(falcon, 0x188 + (port * 16), tag++);

drivers/gpu/drm/nouveau/nvkm/falcon/v1.c

57

nvkm_falcon_wr32(falcon, 0x184 + (port * 16),

drivers/gpu/drm/nouveau/nvkm/falcon/v1.c

64

nvkm_falcon_wr32(falcon, 0x184 + (port * 16), 0);

drivers/gpu/drm/nouveau/nvkm/falcon/v1.c

68

nvkm_falcon_v1_load_dmem(struct nvkm_falcon *falcon, void *data, u32 start,

drivers/gpu/drm/nouveau/nvkm/falcon/v1.c

76

nvkm_falcon_wr32(falcon, 0x1c0 + (port * 8), start | (0x1 << 24));

drivers/gpu/drm/nouveau/nvkm/falcon/v1.c

78

nvkm_falcon_wr32(falcon, 0x1c4 + (port * 8), ((u32 *)data)[i]);

drivers/gpu/drm/nouveau/nvkm/falcon/v1.c

87

nvkm_falcon_wr32(falcon, 0x1c4 + (port * 8),

drivers/gpu/drm/nouveau/nvkm/falcon/v1.c

93

nvkm_falcon_v1_start(struct nvkm_falcon *falcon)

drivers/gpu/drm/nouveau/nvkm/falcon/v1.c

95

u32 reg = nvkm_falcon_rd32(falcon, 0x100);

drivers/gpu/drm/nouveau/nvkm/falcon/v1.c

98

nvkm_falcon_wr32(falcon, 0x130, 0x2);

drivers/gpu/drm/nouveau/nvkm/subdev/acr/base.c

117

ret = nvkm_subdev_ref(rtos->falcon->owner);

drivers/gpu/drm/nouveau/nvkm/subdev/acr/base.c

160

return rtos->func->bootstrap_multiple_falcons(rtos->falcon, mask);

drivers/gpu/drm/nouveau/nvkm/subdev/acr/base.c

163

int ret = rtos->func->bootstrap_falcon(rtos->falcon, id);

drivers/gpu/drm/nouveau/nvkm/subdev/acr/base.c

222

struct nvkm_falcon *falcon;

drivers/gpu/drm/nouveau/nvkm/subdev/acr/base.c

248

ret = nvkm_falcon_get(lsfw->falcon, subdev);

drivers/gpu/drm/nouveau/nvkm/subdev/acr/base.c

252

nvkm_falcon_put(lsfw->falcon, subdev);

drivers/gpu/drm/nouveau/nvkm/subdev/acr/base.c

257

lsf->falcon = lsfw->falcon;

drivers/gpu/drm/nouveau/nvkm/subdev/acr/base.c

341

case NVKM_ACR_HSF_PMU : falcon = &device->pmu->falcon; break;

drivers/gpu/drm/nouveau/nvkm/subdev/acr/base.c

342

case NVKM_ACR_HSF_SEC2: falcon = &device->sec2->falcon; break;

drivers/gpu/drm/nouveau/nvkm/subdev/acr/base.c

343

case NVKM_ACR_HSF_GSP : falcon = &device->gsp->falcon; break;

drivers/gpu/drm/nouveau/nvkm/subdev/acr/base.c

349

ret = nvkm_falcon_fw_oneinit(&hsfw->fw, falcon, acr->vmm, acr->inst);

drivers/gpu/drm/nouveau/nvkm/subdev/acr/base.c

79

nvkm_subdev_unref(acr->rtos->falcon->owner);

drivers/gpu/drm/nouveau/nvkm/subdev/acr/ga102.c

110

.falcon = lsfw->falcon,

drivers/gpu/drm/nouveau/nvkm/subdev/acr/ga102.c

114

ret = nvkm_falcon_get(fw.falcon, &acr->subdev);

drivers/gpu/drm/nouveau/nvkm/subdev/acr/ga102.c

123

nvkm_falcon_put(fw.falcon, &acr->subdev);

drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm200.c

239

flcn_bl_dmem_desc_v1_dump(fw->falcon->user, &hsdesc);

drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm200.c

241

return nvkm_falcon_pio_wr(fw->falcon, (u8 *)&hsdesc, 0, 0, DMEM, 0, sizeof(hsdesc), 0, 0);

drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm200.c

285

struct nvkm_acr *acr = fw->falcon->owner->device->acr;

drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm20b.c

63

flcn_bl_dmem_desc_dump(fw->falcon->user, &hsdesc);

drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm20b.c

65

return nvkm_falcon_pio_wr(fw->falcon, (u8 *)&hsdesc, 0, 0, DMEM, 0, sizeof(hsdesc), 0, 0);

drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm20b.c

73

struct nvkm_acr *acr = fw->falcon->owner->device->acr;

drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp102.c

200

struct nvkm_acr *acr = fw->falcon->owner->device->acr;

drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp108.c

45

flcn_bl_dmem_desc_v2_dump(fw->falcon->user, &hsdesc);

drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp108.c

47

return nvkm_falcon_pio_wr(fw->falcon, (u8 *)&hsdesc, 0, 0, DMEM, 0, sizeof(hsdesc), 0, 0);

drivers/gpu/drm/nouveau/nvkm/subdev/acr/lsfw.c

142

struct nvkm_falcon *falcon,

drivers/gpu/drm/nouveau/nvkm/subdev/acr/lsfw.c

150

lsfw = nvkm_acr_lsfw_load_sig_image_desc_(subdev, falcon, id, path, ver,

drivers/gpu/drm/nouveau/nvkm/subdev/acr/lsfw.c

162

struct nvkm_falcon *falcon,

drivers/gpu/drm/nouveau/nvkm/subdev/acr/lsfw.c

170

lsfw = nvkm_acr_lsfw_load_sig_image_desc_(subdev, falcon, id, path, ver,

drivers/gpu/drm/nouveau/nvkm/subdev/acr/lsfw.c

182

struct nvkm_falcon *falcon,

drivers/gpu/drm/nouveau/nvkm/subdev/acr/lsfw.c

192

lsfw = nvkm_acr_lsfw_load_sig_image_desc_(subdev, falcon, id, path, ver, func, &fw);

drivers/gpu/drm/nouveau/nvkm/subdev/acr/lsfw.c

250

struct nvkm_falcon *falcon,

drivers/gpu/drm/nouveau/nvkm/subdev/acr/lsfw.c

263

if (IS_ERR((lsfw = nvkm_acr_lsfw_add(func, acr, falcon, id))))

drivers/gpu/drm/nouveau/nvkm/subdev/acr/lsfw.c

326

struct nvkm_falcon *falcon,

drivers/gpu/drm/nouveau/nvkm/subdev/acr/lsfw.c

348

if (IS_ERR((lsfw = nvkm_acr_lsfw_add(func, acr, falcon, id))))

drivers/gpu/drm/nouveau/nvkm/subdev/acr/lsfw.c

60

struct nvkm_falcon *falcon, enum nvkm_acr_lsf_id id)

drivers/gpu/drm/nouveau/nvkm/subdev/acr/lsfw.c

82

lsfw->falcon = falcon;

drivers/gpu/drm/nouveau/nvkm/subdev/acr/lsfw.c

88

struct nvkm_falcon *falcon,

drivers/gpu/drm/nouveau/nvkm/subdev/acr/lsfw.c

98

if (IS_ERR((lsfw = nvkm_acr_lsfw_add(func, acr, falcon, id))))

drivers/gpu/drm/nouveau/nvkm/subdev/acr/priv.h

108

struct nvkm_falcon *falcon;

drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm200.c

97

ret = nvkm_falcon_reset(&subdev->device->pmu->falcon);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ga102.c

40

0, &subdev->device->nvdec[0]->falcon, &fb->vpr_scrubber);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp102.c

63

0, &subdev->device->nvdec[0]->falcon, &fb->vpr_scrubber);

drivers/gpu/drm/nouveau/nvkm/subdev/fsp/base.c

36

nvkm_falcon_dtor(&fsp->falcon);

drivers/gpu/drm/nouveau/nvkm/subdev/fsp/base.c

65

return nvkm_falcon_ctor(&nvkm_fsp_flcn, &fsp->subdev, "fsp", 0x8f2000, &fsp->falcon);

drivers/gpu/drm/nouveau/nvkm/subdev/fsp/gh100.c

143

ret = nvkm_falcon_pio_wr(&fsp->falcon, packet, 0, 0, EMEM, 0, packet_size, 0, false);

drivers/gpu/drm/nouveau/nvkm/subdev/fsp/gh100.c

94

ret = nvkm_falcon_pio_rd(&fsp->falcon, 0, EMEM, 0, packet, 0, packet_size);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/base.c

106

nvkm_falcon_dtor(&gsp->falcon);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/base.c

162

&gsp->falcon);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/fwsec.c

185

&gsp->falcon, fw);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/fwsec.c

234

&gsp->falcon, fw);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/fwsec.c

325

ret = nvkm_gsp_fwsec_boot(gsp, &gsp->fws.falcon.sb);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/fwsec.c

342

return nvkm_gsp_fwsec_init(gsp, &gsp->fws.falcon.sb, "fwsec-sb",

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/ga102.c

103

FLCN_DBG(falcon, "brom: %08x %08x", fw->engine_id, fw->ucode_id);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/ga102.c

104

FLCN_DBG(falcon, "sig_fuse_version: %08x", sig_fuse_version);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/ga102.c

113

FLCN_DBG(falcon, "reg_fuse_version: %08x", reg_fuse_version);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/ga102.c

115

FLCN_DBG(falcon, "reg_fuse_version: %08x", reg_fuse_version);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/ga102.c

33

ret = gsp->falcon.func->reset_eng(&gsp->falcon);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/ga102.c

37

nvkm_falcon_mask(&gsp->falcon, 0x1668, 0x00000111, 0x00000111);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/ga102.c

43

struct nvkm_falcon *falcon, struct nvkm_falcon_fw *fw)

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/ga102.c

61

blob->data + hdr->data_offset, hdr->data_size, falcon, fw);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/ga102.c

97

struct nvkm_falcon *falcon = fw->falcon;

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/ga102.c

98

struct nvkm_device *device = falcon->owner->device;

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/gh100.c

22

struct nvkm_falcon *falcon = &gsp->falcon;

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/gh100.c

32

u32 data = nvkm_falcon_rd32(falcon, falcon->addr2 + NV_PRISCV_RISCV_CPUCTL);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/gh100.c

49

*mbox0 = nvkm_falcon_rd32(&gsp->falcon, NV_PFALCON_FALCON_MAILBOX0);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/gh100.c

56

u32 mbox1 = nvkm_falcon_rd32(&gsp->falcon, NV_PFALCON_FALCON_MAILBOX1);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/gh100.c

64

data = nvkm_falcon_rd32(&gsp->falcon, NV_PFALCON_FALCON_HWCFG2);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gsp.c

1073

nvkm_falcon_reset(&gsp->falcon);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gsp.c

1074

nvkm_falcon_mask(&gsp->falcon, 0x624, 0x00000080, 0x00000080);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gsp.c

1075

nvkm_falcon_wr32(&gsp->falcon, 0x10c, 0x00000000);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gsp.c

1079

if (nvkm_falcon_rd32(&gsp->falcon, 0x100) & 0x00000040)

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gsp.c

1080

nvkm_falcon_wr32(&gsp->falcon, 0x130, 0x00000002);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gsp.c

1082

nvkm_falcon_wr32(&gsp->falcon, 0x100, 0x00000002);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gsp.c

1087

if (nvkm_falcon_rd32(&gsp->falcon, 0x100) & 0x00000010)

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gsp.c

1101

nvkm_falcon_wr32(&gsp->falcon, 0x040, lower_32_bits(gsp->libos.addr));

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gsp.c

1102

nvkm_falcon_wr32(&gsp->falcon, 0x044, upper_32_bits(gsp->libos.addr));

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gsp.c

1104

nvkm_falcon_start(&sec2->falcon);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gsp.c

1112

mbox0 = nvkm_falcon_rd32(&sec2->falcon, 0x040);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gsp.c

1118

nvkm_falcon_wr32(&gsp->falcon, 0x080, gsp->boot.app_version);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gsp.c

1120

if (WARN_ON(!nvkm_falcon_riscv_active(&gsp->falcon)))

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gsp.c

1772

if (nvkm_falcon_rd32(&gsp->falcon, 0x040) == 0x80000000)

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gsp.c

1785

nvkm_falcon_wr32(&gsp->falcon, 0x080, gsp->boot.app_version);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gsp.c

1787

if (WARN_ON(!nvkm_falcon_riscv_active(&gsp->falcon)))

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gsp.c

64

u32 intr = nvkm_falcon_rd32(&gsp->falcon, 0x0008);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gsp.c

65

u32 inte = nvkm_falcon_rd32(&gsp->falcon, gsp->falcon.func->addr2 +

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gsp.c

66

gsp->falcon.func->riscv_irqmask);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gsp.c

75

nvkm_falcon_wr32(&gsp->falcon, 0x004, 0x00000040);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gsp.c

82

nvkm_falcon_wr32(&gsp->falcon, 0x014, stat);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gsp.c

83

nvkm_falcon_wr32(&gsp->falcon, 0x004, stat);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gsp.c

86

nvkm_falcon_intr_retrigger(&gsp->falcon);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/rpc.c

413

nvkm_falcon_wr32(&gsp->falcon, 0xc00, 0x00000000);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/tu102.c

142

flcn_bl_dmem_desc_v2_dump(fw->falcon->user, &desc);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/tu102.c

144

nvkm_falcon_mask(fw->falcon, 0x600 + desc.ctx_dma * 4, 0x00000007, 0x00000005);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/tu102.c

146

return nvkm_falcon_pio_wr(fw->falcon, (u8 *)&desc, 0, 0, DMEM, 0, sizeof(desc), 0, 0);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/tu102.c

160

return gsp->falcon.func->reset_eng(&gsp->falcon);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/tu102.c

173

nvkm_falcon_reset(&gsp->falcon);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/tu102.c

308

&device->sec2->falcon, &gsp->booter.load);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/tu102.c

313

&device->sec2->falcon, &gsp->booter.unload);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/tu102.c

355

nvkm_falcon_wr32(&gsp->falcon, 0x040, lower_32_bits(gsp->libos.addr));

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/tu102.c

356

nvkm_falcon_wr32(&gsp->falcon, 0x044, upper_32_bits(gsp->libos.addr));

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/tu102.c

42

nvkm_falcon_fw_dtor(&gsp->fws.falcon.sb);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/tu102.c

78

struct nvkm_falcon *falcon, struct nvkm_falcon_fw *fw)

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/tu102.c

95

blob->data + hdr->data_offset, hdr->data_size, falcon, fw);

drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c

112

nvkm_falcon_dtor(&pmu->falcon);

drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c

145

0x10a000, &pmu->falcon);

drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c

149

if ((ret = nvkm_falcon_qmgr_new(&pmu->falcon, &pmu->qmgr)) ||

drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c

100

status->busy = nvkm_falcon_rd32(falcon, 0x508 + (BUSY_SLOT * 0x10));

drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c

101

status->total= nvkm_falcon_rd32(falcon, 0x508 + (CLK_SLOT * 0x10));

drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c

107

struct nvkm_falcon *falcon = &pmu->base.falcon;

drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c

109

nvkm_falcon_wr32(falcon, 0x508 + (BUSY_SLOT * 0x10), 0x80000000);

drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c

110

nvkm_falcon_wr32(falcon, 0x508 + (CLK_SLOT * 0x10), 0x80000000);

drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c

163

nvkm_falcon_put(&pmu->falcon, &pmu->subdev);

drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c

172

struct nvkm_falcon *falcon = &pmu->falcon;

drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c

175

ret = nvkm_falcon_get(falcon, subdev);

drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c

177

nvkm_error(subdev, "cannot acquire %s falcon!\n", falcon->name);

drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c

182

nvkm_falcon_wr32(falcon, 0x504 + (BUSY_SLOT * 0x10), 0x00200001);

drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c

183

nvkm_falcon_wr32(falcon, 0x50c + (BUSY_SLOT * 0x10), 0x00000002);

drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c

184

nvkm_falcon_wr32(falcon, 0x50c + (CLK_SLOT * 0x10), 0x00000003);

drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c

98

struct nvkm_falcon *falcon = &pmu->base.falcon;

drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm200.c

27

gm200_pmu_flcn_bind_stat(struct nvkm_falcon *falcon, bool intr)

drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm200.c

29

nvkm_falcon_wr32(falcon, 0x200, 0x0000030e);

drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm200.c

30

return (nvkm_falcon_rd32(falcon, 0x20c) & 0x00007000) >> 12;

drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm200.c

34

gm200_pmu_flcn_bind_inst(struct nvkm_falcon *falcon, int target, u64 addr)

drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm200.c

36

nvkm_falcon_wr32(falcon, 0xe00, 4); /* DMAIDX_UCODE */

drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm200.c

37

nvkm_falcon_wr32(falcon, 0xe04, 0); /* DMAIDX_VIRT */

drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm200.c

38

nvkm_falcon_wr32(falcon, 0xe08, 4); /* DMAIDX_PHYS_VID */

drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm200.c

39

nvkm_falcon_wr32(falcon, 0xe0c, 5); /* DMAIDX_PHYS_SYS_COH */

drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm200.c

40

nvkm_falcon_wr32(falcon, 0xe10, 6); /* DMAIDX_PHYS_SYS_NCOH */

drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm200.c

41

nvkm_falcon_mask(falcon, 0x090, 0x00010000, 0x00010000);

drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm200.c

42

nvkm_falcon_wr32(falcon, 0x480, (1 << 30) | (target << 28) | (addr >> 12));

drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c

103

.argv = lsfw->falcon->data.limit - sizeof(struct nv_pmu_args),

drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c

211

nvkm_falcon_put(&pmu->falcon, &pmu->subdev);

drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c

217

struct nvkm_falcon *falcon = &pmu->falcon;

drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c

219

u32 addr_args = falcon->data.limit - sizeof(args);

drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c

222

ret = nvkm_falcon_get(&pmu->falcon, &pmu->subdev);

drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c

228

nvkm_falcon_pio_wr(falcon, (u8 *)&args, 0, 0, DMEM, addr_args, sizeof(args), 0, false);

drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c

229

nvkm_falcon_start(falcon);

drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c

253

return nvkm_acr_lsfw_load_sig_image_desc(&pmu->subdev, &pmu->falcon,

drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c

39

gm20b_pmu_acr_bootstrap_falcon(struct nvkm_falcon *falcon,

drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c

42

struct nvkm_pmu *pmu = container_of(falcon, typeof(*pmu), falcon);

drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp10b.c

38

gp10b_pmu_acr_bootstrap_multiple_falcons(struct nvkm_falcon *falcon, u32 mask)

drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp10b.c

40

struct nvkm_pmu *pmu = container_of(falcon, typeof(*pmu), falcon);

drivers/gpu/drm/tegra/falcon.c

103

dev_err(falcon->dev, "unsupported firmware version\n");

drivers/gpu/drm/tegra/falcon.c

108

if (bin->size > falcon->firmware.size) {

drivers/gpu/drm/tegra/falcon.c

109

dev_err(falcon->dev, "firmware image size inconsistency\n");

drivers/gpu/drm/tegra/falcon.c

113

os = falcon->firmware.virt + bin->os_header_offset;

drivers/gpu/drm/tegra/falcon.c

115

falcon->firmware.bin_data.size = bin->os_size;

drivers/gpu/drm/tegra/falcon.c

116

falcon->firmware.bin_data.offset = bin->os_data_offset;

drivers/gpu/drm/tegra/falcon.c

117

falcon->firmware.code.offset = os->code_offset;

drivers/gpu/drm/tegra/falcon.c

118

falcon->firmware.code.size = os->code_size;

drivers/gpu/drm/tegra/falcon.c

119

falcon->firmware.data.offset = os->data_offset;

drivers/gpu/drm/tegra/falcon.c

120

falcon->firmware.data.size = os->data_size;

drivers/gpu/drm/tegra/falcon.c

125

int falcon_read_firmware(struct falcon *falcon, const char *name)

drivers/gpu/drm/tegra/falcon.c

130

err = request_firmware(&falcon->firmware.firmware, name, falcon->dev);

drivers/gpu/drm/tegra/falcon.c

134

falcon->firmware.size = falcon->firmware.firmware->size;

drivers/gpu/drm/tegra/falcon.c

139

int falcon_load_firmware(struct falcon *falcon)

drivers/gpu/drm/tegra/falcon.c

141

const struct firmware *firmware = falcon->firmware.firmware;

drivers/gpu/drm/tegra/falcon.c

145

falcon_copy_firmware_image(falcon, firmware);

drivers/gpu/drm/tegra/falcon.c

148

err = falcon_parse_firmware_image(falcon);

drivers/gpu/drm/tegra/falcon.c

150

dev_err(falcon->dev, "failed to parse firmware image\n");

drivers/gpu/drm/tegra/falcon.c

155

falcon->firmware.firmware = NULL;

drivers/gpu/drm/tegra/falcon.c

160

int falcon_init(struct falcon *falcon)

drivers/gpu/drm/tegra/falcon.c

162

falcon->firmware.virt = NULL;

drivers/gpu/drm/tegra/falcon.c

167

void falcon_exit(struct falcon *falcon)

drivers/gpu/drm/tegra/falcon.c

169

if (falcon->firmware.firmware)

drivers/gpu/drm/tegra/falcon.c

170

release_firmware(falcon->firmware.firmware);

drivers/gpu/drm/tegra/falcon.c

173

int falcon_boot(struct falcon *falcon)

drivers/gpu/drm/tegra/falcon.c

179

if (!falcon->firmware.virt)

drivers/gpu/drm/tegra/falcon.c

182

err = readl_poll_timeout(falcon->regs + FALCON_DMACTL, value,

drivers/gpu/drm/tegra/falcon.c

189

falcon_writel(falcon, 0, FALCON_DMACTL);

drivers/gpu/drm/tegra/falcon.c

192

falcon_writel(falcon, (falcon->firmware.iova +

drivers/gpu/drm/tegra/falcon.c

193

falcon->firmware.bin_data.offset) >> 8,

drivers/gpu/drm/tegra/falcon.c

197

for (offset = 0; offset < falcon->firmware.data.size; offset += 256)

drivers/gpu/drm/tegra/falcon.c

198

falcon_copy_chunk(falcon,

drivers/gpu/drm/tegra/falcon.c

199

falcon->firmware.data.offset + offset,

drivers/gpu/drm/tegra/falcon.c

20

static void falcon_writel(struct falcon *falcon, u32 value, u32 offset)

drivers/gpu/drm/tegra/falcon.c

203

for (offset = 0; offset < falcon->firmware.code.size; offset += 256)

drivers/gpu/drm/tegra/falcon.c

204

falcon_copy_chunk(falcon, falcon->firmware.code.offset + offset,

drivers/gpu/drm/tegra/falcon.c

208

err = falcon_dma_wait_idle(falcon);

drivers/gpu/drm/tegra/falcon.c

213

falcon_writel(falcon, FALCON_IRQMSET_EXT(0xff) |

drivers/gpu/drm/tegra/falcon.c

22

writel(value, falcon->regs + offset);

drivers/gpu/drm/tegra/falcon.c

220

falcon_writel(falcon, FALCON_IRQDEST_EXT(0xff) |

drivers/gpu/drm/tegra/falcon.c

228

falcon_writel(falcon, FALCON_ITFEN_MTHDEN |

drivers/gpu/drm/tegra/falcon.c

233

falcon_writel(falcon, 0x00000000, FALCON_BOOTVEC);

drivers/gpu/drm/tegra/falcon.c

234

falcon_writel(falcon, FALCON_CPUCTL_STARTCPU, FALCON_CPUCTL);

drivers/gpu/drm/tegra/falcon.c

236

err = falcon_wait_idle(falcon);

drivers/gpu/drm/tegra/falcon.c

238

dev_err(falcon->dev, "Falcon boot failed due to timeout\n");

drivers/gpu/drm/tegra/falcon.c

245

void falcon_execute_method(struct falcon *falcon, u32 method, u32 data)

drivers/gpu/drm/tegra/falcon.c

247

falcon_writel(falcon, method >> 2, FALCON_UCLASS_METHOD_OFFSET);

drivers/gpu/drm/tegra/falcon.c

248

falcon_writel(falcon, data, FALCON_UCLASS_METHOD_DATA);

drivers/gpu/drm/tegra/falcon.c

25

int falcon_wait_idle(struct falcon *falcon)

drivers/gpu/drm/tegra/falcon.c

29

return readl_poll_timeout(falcon->regs + FALCON_IDLESTATE, value,

drivers/gpu/drm/tegra/falcon.c

33

static int falcon_dma_wait_not_full(struct falcon *falcon)

drivers/gpu/drm/tegra/falcon.c

37

return readl_poll_timeout(falcon->regs + FALCON_DMATRFCMD, value,

drivers/gpu/drm/tegra/falcon.c

41

static int falcon_dma_wait_idle(struct falcon *falcon)

drivers/gpu/drm/tegra/falcon.c

45

return readl_poll_timeout(falcon->regs + FALCON_DMATRFCMD, value,

drivers/gpu/drm/tegra/falcon.c

49

static int falcon_copy_chunk(struct falcon *falcon,

drivers/gpu/drm/tegra/falcon.c

68

err = falcon_dma_wait_not_full(falcon);

drivers/gpu/drm/tegra/falcon.c

72

falcon_writel(falcon, offset, FALCON_DMATRFMOFFS);

drivers/gpu/drm/tegra/falcon.c

73

falcon_writel(falcon, base, FALCON_DMATRFFBOFFS);

drivers/gpu/drm/tegra/falcon.c

74

falcon_writel(falcon, cmd, FALCON_DMATRFCMD);

drivers/gpu/drm/tegra/falcon.c

79

static void falcon_copy_firmware_image(struct falcon *falcon,

drivers/gpu/drm/tegra/falcon.c

82

u32 *virt = falcon->firmware.virt;

drivers/gpu/drm/tegra/falcon.c

90

static int falcon_parse_firmware_image(struct falcon *falcon)

drivers/gpu/drm/tegra/falcon.c

92

struct falcon_fw_bin_header_v1 *bin = (void *)falcon->firmware.virt;

drivers/gpu/drm/tegra/falcon.c

97

dev_err(falcon->dev, "incorrect firmware magic\n");

drivers/gpu/drm/tegra/falcon.h

108

int falcon_init(struct falcon *falcon);

drivers/gpu/drm/tegra/falcon.h

109

void falcon_exit(struct falcon *falcon);

drivers/gpu/drm/tegra/falcon.h

110

int falcon_read_firmware(struct falcon *falcon, const char *firmware_name);

drivers/gpu/drm/tegra/falcon.h

111

int falcon_load_firmware(struct falcon *falcon);

drivers/gpu/drm/tegra/falcon.h

112

int falcon_boot(struct falcon *falcon);

drivers/gpu/drm/tegra/falcon.h

113

void falcon_execute_method(struct falcon *falcon, u32 method, u32 data);

drivers/gpu/drm/tegra/falcon.h

114

int falcon_wait_idle(struct falcon *falcon);

drivers/gpu/drm/tegra/nvdec.c

225

dma_unmap_single(nvdec->dev, nvdec->falcon.firmware.phys,

drivers/gpu/drm/tegra/nvdec.c

226

nvdec->falcon.firmware.size, DMA_TO_DEVICE);

drivers/gpu/drm/tegra/nvdec.c

227

tegra_drm_free(tegra, nvdec->falcon.firmware.size,

drivers/gpu/drm/tegra/nvdec.c

228

nvdec->falcon.firmware.virt,

drivers/gpu/drm/tegra/nvdec.c

229

nvdec->falcon.firmware.iova);

drivers/gpu/drm/tegra/nvdec.c

231

dma_free_coherent(nvdec->dev, nvdec->falcon.firmware.size,

drivers/gpu/drm/tegra/nvdec.c

232

nvdec->falcon.firmware.virt,

drivers/gpu/drm/tegra/nvdec.c

233

nvdec->falcon.firmware.iova);

drivers/gpu/drm/tegra/nvdec.c

253

if (nvdec->falcon.firmware.virt)

drivers/gpu/drm/tegra/nvdec.c

256

err = falcon_read_firmware(&nvdec->falcon, nvdec->config->firmware);

drivers/gpu/drm/tegra/nvdec.c

260

size = nvdec->falcon.firmware.size;

drivers/gpu/drm/tegra/nvdec.c

272

nvdec->falcon.firmware.virt = virt;

drivers/gpu/drm/tegra/nvdec.c

273

nvdec->falcon.firmware.iova = iova;

drivers/gpu/drm/tegra/nvdec.c

275

err = falcon_load_firmware(&nvdec->falcon);

drivers/gpu/drm/tegra/nvdec.c

293

nvdec->falcon.firmware.phys = phys;

drivers/gpu/drm/tegra/nvdec.c

37

struct falcon falcon;

drivers/gpu/drm/tegra/nvdec.c

505

nvdec->falcon.dev = dev;

drivers/gpu/drm/tegra/nvdec.c

506

nvdec->falcon.regs = nvdec->regs;

drivers/gpu/drm/tegra/nvdec.c

508

err = falcon_init(&nvdec->falcon);

drivers/gpu/drm/tegra/nvdec.c

540

falcon_exit(&nvdec->falcon);

drivers/gpu/drm/tegra/nvdec.c

551

falcon_exit(&nvdec->falcon);

drivers/gpu/drm/tegra/nvdec.c

81

err = falcon_boot(&nvdec->falcon);

drivers/gpu/drm/tegra/nvdec.c

85

err = falcon_wait_idle(&nvdec->falcon);

drivers/gpu/drm/tegra/nvjpg.c

119

if (nvjpg->falcon.firmware.virt)

drivers/gpu/drm/tegra/nvjpg.c

122

err = falcon_read_firmware(&nvjpg->falcon, nvjpg->config->firmware);

drivers/gpu/drm/tegra/nvjpg.c

126

size = nvjpg->falcon.firmware.size;

drivers/gpu/drm/tegra/nvjpg.c

138

nvjpg->falcon.firmware.virt = virt;

drivers/gpu/drm/tegra/nvjpg.c

139

nvjpg->falcon.firmware.iova = iova;

drivers/gpu/drm/tegra/nvjpg.c

141

err = falcon_load_firmware(&nvjpg->falcon);

drivers/gpu/drm/tegra/nvjpg.c

159

nvjpg->falcon.firmware.phys = phys;

drivers/gpu/drm/tegra/nvjpg.c

188

err = falcon_boot(&nvjpg->falcon);

drivers/gpu/drm/tegra/nvjpg.c

22

struct falcon falcon;

drivers/gpu/drm/tegra/nvjpg.c

268

nvjpg->falcon.dev = dev;

drivers/gpu/drm/tegra/nvjpg.c

269

nvjpg->falcon.regs = nvjpg->regs;

drivers/gpu/drm/tegra/nvjpg.c

271

err = falcon_init(&nvjpg->falcon);

drivers/gpu/drm/tegra/nvjpg.c

300

falcon_exit(&nvjpg->falcon);

drivers/gpu/drm/tegra/nvjpg.c

310

falcon_exit(&nvjpg->falcon);

drivers/gpu/drm/tegra/nvjpg.c

91

dma_unmap_single(nvjpg->dev, nvjpg->falcon.firmware.phys,

drivers/gpu/drm/tegra/nvjpg.c

92

nvjpg->falcon.firmware.size, DMA_TO_DEVICE);

drivers/gpu/drm/tegra/nvjpg.c

93

tegra_drm_free(tegra, nvjpg->falcon.firmware.size,

drivers/gpu/drm/tegra/nvjpg.c

94

nvjpg->falcon.firmware.virt,

drivers/gpu/drm/tegra/nvjpg.c

95

nvjpg->falcon.firmware.iova);

drivers/gpu/drm/tegra/nvjpg.c

97

dma_free_coherent(nvjpg->dev, nvjpg->falcon.firmware.size,

drivers/gpu/drm/tegra/nvjpg.c

98

nvjpg->falcon.firmware.virt,

drivers/gpu/drm/tegra/nvjpg.c

99

nvjpg->falcon.firmware.iova);

drivers/gpu/drm/tegra/vic.c

101

falcon_execute_method(&vic->falcon, VIC_SET_FCE_UCODE_SIZE,

drivers/gpu/drm/tegra/vic.c

104

&vic->falcon, VIC_SET_FCE_UCODE_OFFSET,

drivers/gpu/drm/tegra/vic.c

105

(vic->falcon.firmware.iova + fce_bin_data_offset) >> 8);

drivers/gpu/drm/tegra/vic.c

108

err = falcon_wait_idle(&vic->falcon);

drivers/gpu/drm/tegra/vic.c

191

dma_unmap_single(vic->dev, vic->falcon.firmware.phys,

drivers/gpu/drm/tegra/vic.c

192

vic->falcon.firmware.size, DMA_TO_DEVICE);

drivers/gpu/drm/tegra/vic.c

193

tegra_drm_free(tegra, vic->falcon.firmware.size,

drivers/gpu/drm/tegra/vic.c

194

vic->falcon.firmware.virt,

drivers/gpu/drm/tegra/vic.c

195

vic->falcon.firmware.iova);

drivers/gpu/drm/tegra/vic.c

197

dma_free_coherent(vic->dev, vic->falcon.firmware.size,

drivers/gpu/drm/tegra/vic.c

198

vic->falcon.firmware.virt,

drivers/gpu/drm/tegra/vic.c

199

vic->falcon.firmware.iova);

drivers/gpu/drm/tegra/vic.c

223

if (vic->falcon.firmware.virt) {

drivers/gpu/drm/tegra/vic.c

228

err = falcon_read_firmware(&vic->falcon, vic->config->firmware);

drivers/gpu/drm/tegra/vic.c

232

size = vic->falcon.firmware.size;

drivers/gpu/drm/tegra/vic.c

248

vic->falcon.firmware.virt = virt;

drivers/gpu/drm/tegra/vic.c

249

vic->falcon.firmware.iova = iova;

drivers/gpu/drm/tegra/vic.c

251

err = falcon_load_firmware(&vic->falcon);

drivers/gpu/drm/tegra/vic.c

269

vic->falcon.firmware.phys = phys;

drivers/gpu/drm/tegra/vic.c

30

struct falcon falcon;

drivers/gpu/drm/tegra/vic.c

496

vic->falcon.dev = dev;

drivers/gpu/drm/tegra/vic.c

497

vic->falcon.regs = vic->regs;

drivers/gpu/drm/tegra/vic.c

499

err = falcon_init(&vic->falcon);

drivers/gpu/drm/tegra/vic.c

530

falcon_exit(&vic->falcon);

drivers/gpu/drm/tegra/vic.c

541

falcon_exit(&vic->falcon);

drivers/gpu/drm/tegra/vic.c

88

err = falcon_boot(&vic->falcon);

drivers/gpu/drm/tegra/vic.c

92

hdr = vic->falcon.firmware.virt;

drivers/gpu/drm/tegra/vic.c

97

hdr = vic->falcon.firmware.virt +

drivers/video/fbdev/atafb.c

1011

par->hw.falcon.line_width = bpp * xres / 16;

drivers/video/fbdev/atafb.c

1012

par->hw.falcon.line_offset = bpp * (xres_virtual - xres) / 16;

drivers/video/fbdev/atafb.c

1024

par->hw.falcon.ste_mode = 1;

drivers/video/fbdev/atafb.c

1025

par->hw.falcon.f_shift = 0x000;

drivers/video/fbdev/atafb.c

1026

par->hw.falcon.st_shift = 0x200;

drivers/video/fbdev/atafb.c

1158

par->hw.falcon.vid_control = mon_type | f030_bus_width;

drivers/video/fbdev/atafb.c

1160

par->hw.falcon.vid_control |= VCO_SHORTOFFS; /* base_offset 64 */

drivers/video/fbdev/atafb.c

1162

par->hw.falcon.vid_control |= VCO_HSYPOS;

drivers/video/fbdev/atafb.c

1164

par->hw.falcon.vid_control |= VCO_VSYPOS;

drivers/video/fbdev/atafb.c

1166

par->hw.falcon.vid_control |= pclock->control_mask;

drivers/video/fbdev/atafb.c

1168

par->hw.falcon.sync = pclock->sync_mask | 0x2;

drivers/video/fbdev/atafb.c

1170

par->hw.falcon.vid_mode = (2 / plen) << 2;

drivers/video/fbdev/atafb.c

1172

par->hw.falcon.vid_mode |= VMO_DOUBLE;

drivers/video/fbdev/atafb.c

1174

par->hw.falcon.vid_mode |= VMO_INTER;

drivers/video/fbdev/atafb.c

1198

prescale = hxx_prescale(&par->hw.falcon);

drivers/video/fbdev/atafb.c

1199

base_off = par->hw.falcon.vid_control & VCO_SHORTOFFS ? 64 : 128;

drivers/video/fbdev/atafb.c

1205

if (par->hw.falcon.f_shift & 0x100) {

drivers/video/fbdev/atafb.c

1212

if (par->hw.falcon.ste_mode)

drivers/video/fbdev/atafb.c

127

} falcon;

drivers/video/fbdev/atafb.c

1342

par->hw.falcon.xoffset = 0;

drivers/video/fbdev/atafb.c

1356

struct falcon_hw *hw = &par->hw.falcon;

drivers/video/fbdev/atafb.c

139

#define HHT hw.falcon.hht

drivers/video/fbdev/atafb.c

140

#define HBB hw.falcon.hbb

drivers/video/fbdev/atafb.c

141

#define HBE hw.falcon.hbe

drivers/video/fbdev/atafb.c

142

#define HDB hw.falcon.hdb

drivers/video/fbdev/atafb.c

143

#define HDE hw.falcon.hde

drivers/video/fbdev/atafb.c

144

#define HSS hw.falcon.hss

drivers/video/fbdev/atafb.c

145

#define VFT hw.falcon.vft

drivers/video/fbdev/atafb.c

146

#define VBB hw.falcon.vbb

drivers/video/fbdev/atafb.c

147

#define VBE hw.falcon.vbe

drivers/video/fbdev/atafb.c

148

#define VDB hw.falcon.vdb

drivers/video/fbdev/atafb.c

149

#define VDE hw.falcon.vde

drivers/video/fbdev/atafb.c

150

#define VSS hw.falcon.vss

drivers/video/fbdev/atafb.c

1518

struct falcon_hw *hw = &par->hw.falcon;

drivers/video/fbdev/atafb.c

1570

f_new_mode = par->hw.falcon;

drivers/video/fbdev/atafb.c

1626

videl.xoffset = current_par.hw.falcon.xoffset;

drivers/video/fbdev/atafb.c

1627

shifter_f030.off_next = current_par.hw.falcon.line_offset;

drivers/video/fbdev/atafb.c

1643

par->hw.falcon.xoffset = var->xoffset & 15;

drivers/video/fbdev/atafb.c

1645

par->hw.falcon.xoffset = 0;

drivers/video/fbdev/atafb.c

1648

par->hw.falcon.line_offset = bpp *

drivers/video/fbdev/atafb.c

1650

if (par->hw.falcon.xoffset)

drivers/video/fbdev/atafb.c

1651

par->hw.falcon.line_offset -= bpp;

drivers/video/fbdev/atafb.c

1652

xoffset = var->xoffset - par->hw.falcon.xoffset;

drivers/video/fbdev/atafb.c

3115

fb_info.pseudo_palette = current_par.hw.falcon.pseudo_palette;

drivers/video/fbdev/atafb.c

863

if (par->hw.falcon.mono) {

drivers/video/fbdev/atafb.c

868

} else if (par->hw.falcon.f_shift & 0x100) {

drivers/video/fbdev/atafb.c

932

par->hw.falcon.f_shift = 0x400;

drivers/video/fbdev/atafb.c

933

par->hw.falcon.st_shift = 0x200;

drivers/video/fbdev/atafb.c

936

par->hw.falcon.f_shift = 0x000;

drivers/video/fbdev/atafb.c

937

par->hw.falcon.st_shift = 0x100;

drivers/video/fbdev/atafb.c

940

par->hw.falcon.f_shift = 0x000;

drivers/video/fbdev/atafb.c

941

par->hw.falcon.st_shift = 0x000;

drivers/video/fbdev/atafb.c

944

par->hw.falcon.f_shift = 0x010;

drivers/video/fbdev/atafb.c

947

par->hw.falcon.f_shift = 0x100; /* hicolor, no overlay */

drivers/video/fbdev/atafb.c

950

par->hw.falcon.bpp = bpp;

drivers/video/fbdev/atafb.c

977

par->hw.falcon.ste_mode = bpp == 2;

drivers/video/fbdev/atafb.c

978

par->hw.falcon.mono = bpp == 1;

drivers/video/fbdev/atafb.c

988

if (par->hw.falcon.ste_mode)