f_min
int f_max, f_min;
f_min = f_max - ROUNDING;
if ((speed <= f_max) && (speed >= f_min))
data->fan[f_min][0] = rv;
data->fan[f_min][1] = rv;
min = FAN_FROM_REG(data->fan[f_min][nr],
data->fan[f_min][nr] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr]));
data->fan[f_min][nr]);
static SENSOR_DEVICE_ATTR_2_RW(fan1_min, fan, f_min, 0);
static SENSOR_DEVICE_ATTR_2_RW(fan2_min, fan, f_min, 1);
data->fan[f_min][0] = lm80_read_value(client, LM80_REG_FAN_MIN(1));
data->fan[f_min][1] = lm80_read_value(client, LM80_REG_FAN_MIN(2));
u32 f_min, u32 f_max)
&& (f_min < (pAS_Info->f_if1_Center + (pAS_Info->f_if1_bw / 2)))
&& (f_min < f_max)) {
while ((pNode != NULL) && (pNode->max_ < f_min)) {
if (f_min < pNode->min_)
pNode->min_ = f_min;
pNode->min_ = f_min;
if (!mmc_rescan_try_freq(host, max(freq, host->f_min)))
if (freqs[i] <= host->f_min)
host->f_init = max(min(freqs[0], host->f_max), host->f_min);
WARN_ON(hz && hz < host->f_min);
if (val != 0 && (val > host->f_max || val < host->f_min))
mmc->f_min = AU6601_MIN_CLOCK;
mmc->f_min = DIV_ROUND_UP(host->bus_hz, 512);
mmc->f_min = 450000;
mmc->f_min = host->max_clk / SDCDIV_MAX_CDIV;
mmc->f_max, mmc->f_min, mmc->max_busy_timeout);
slot->clock = mmc->f_min;
clock = max(clock, mmc->f_min);
cvm_mmc_set_clock(slot, slot->mmc->f_min);
mmc->f_min = 400000;
mmc->f_min = val >> cb710_clock_divider_log2[CB710_MAX_DIVIDER_IDX];
mmc->f_min = 312500;
slot->mmc->f_min == clock)
mmc->f_min = host->minimum_speed;
mmc->f_min = DW_MCI_FREQ_MIN;
mmc->f_min = mmc->f_max / 128;
mmc->f_min = 12.5e6;
mmc->f_min = DIV_ROUND_UP(host->current_clk, 256);
host->mmc->f_min = clk_round_rate(host->mmc_clk, 400000);
ret = clk_set_rate(host->mmc_clk, host->mmc->f_min);
mmc->f_min = clk_round_rate(host->sd_clk, 1);
mmc->f_min = clk_round_rate(host->cfg_div_clk, 1);
mmc->f_min = max(spi->controller->min_speed_hz, 400000);
mmc->f_min = DIV_ROUND_UP(host->mclk, 257);
mmc->f_min = DIV_ROUND_UP(host->mclk, 2046);
mmc->f_min = clk_round_rate(host->clk, 100000);
mmc->f_min = DIV_ROUND_UP(host->mclk, 512);
mmc->f_min = DIV_ROUND_CLOSEST(host->sysclk, CLK_DIV_MASK * 2);
mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255);
mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095);
mmc->f_min = DIV_ROUND_UP(host->base_clock, MVSD_BASE_DIV_MAX);
mmc->f_min = clk_get_rate(host->clk_per) >> 16;
mmc->f_min = 400000;
mmc->f_min = 400000;
mmc->f_min = OMAP_MMC_MIN_CLOCK;
mmc->f_min = 100000;
mmc->f_min = (host->clkrate + 63) / 64;
mmc->f_min = max(clk_round_rate(priv->clk, 1) / 512, 1L);
mmc->f_min = 250000;
mmc->f_min = 250000;
mmc->f_min = host->ops->get_min_clock(host);
mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
mmc->f_min = 450000;
unsigned int f_max, f_min = 0, f_min_old;
f_min = clk_round_rate(host->clk, f_min_old / 2);
if (f_min == f_min_old)
f_min_old = f_min;
host->mmc->f_min = f_min >> fls(host->clkdiv_map);
host->mmc->f_min = clk / 512;
host->mmc->f_max, host->mmc->f_min);
int f_min = host->mmc->f_min;
if (clk < f_min)
clk = f_min;
mmc->f_min = SPMMC_MIN_CLK;
mmc->f_min = 400000;
mmc->f_min = 20000000 / 60;
if (mmc->f_min == 0)
mmc->f_min = HCLK / 512;
mmc->f_min = priv->clk_rate / 1024;
mmc->f_min = priv->clk_rate / 512;
mmc->f_min = host->imclk / 512;
mmc->f_min = 400000;
mmc->f_min = VIA_CRDR_MIN_CLOCK;
mmc->f_min = 200000;
mmc->f_min = 375000;
unsigned int f_min;
.f_min = 390425,
mmc->f_min = wmt_caps->f_min;
host->ios.clock = host->f_min;
mmc->f_min = le32_to_cpu(response.f_min);
u32 f_min, f_max;
f_min = ufs->pclk_avail_min;
} while (pclk_rate >= f_min);
if (unlikely(pclk_rate < f_min || pclk_rate > f_max)) {
__le32 f_min;
unsigned int f_min;