CHAN
dwc->ch_regs = &__dw_regs(dw)->CHAN[i];
struct dw_dma_chan_regs CHAN[DW_DMA_MAX_NR_CHANNELS];
dc->ch_regs = &__txx9dmac_regs(dc->ddev)->CHAN[ch];
dc->ch_regs = &__txx9dmac_regs32(dc->ddev)->CHAN[ch];
struct txx9dmac_cregs CHAN[TXX9_DMA_MAX_NR_CHANNELS];
struct txx9dmac_cregs32 CHAN[TXX9_DMA_MAX_NR_CHANNELS];
#define ESR_RXTX_TUNING_H(CHAN) (ESR_BASE + 0x0083 + (CHAN) * 0x10)
#define ESR_RX_SYNCCHAR_L(CHAN) (ESR_BASE + 0x0084 + (CHAN) * 0x10)
#define ESR_RX_SYNCCHAR_H(CHAN) (ESR_BASE + 0x0085 + (CHAN) * 0x10)
#define ESR_RXTX_TEST_L(CHAN) (ESR_BASE + 0x0086 + (CHAN) * 0x10)
#define ESR_RXTX_TEST_H(CHAN) (ESR_BASE + 0x0087 + (CHAN) * 0x10)
#define ESR_GLUE_CTRL0_L(CHAN) (ESR_BASE + 0x0088 + (CHAN) * 0x10)
#define ESR_GLUE_CTRL0_H(CHAN) (ESR_BASE + 0x0089 + (CHAN) * 0x10)
#define ESR_GLUE_CTRL1_L(CHAN) (ESR_BASE + 0x008a + (CHAN) * 0x10)
#define ESR_GLUE_CTRL1_H(CHAN) (ESR_BASE + 0x008b + (CHAN) * 0x10)
#define ESR_RXTX_TUNING1_L(CHAN) (ESR_BASE + 0x00c2 + (CHAN) * 0x10)
#define ESR_RXTX_TUNING1_H(CHAN) (ESR_BASE + 0x00c2 + (CHAN) * 0x10)
#define ESR_RXTX_TUNING2_L(CHAN) (ESR_BASE + 0x0102 + (CHAN) * 0x10)
#define ESR_RXTX_TUNING2_H(CHAN) (ESR_BASE + 0x0102 + (CHAN) * 0x10)
#define ESR_RXTX_TUNING3_L(CHAN) (ESR_BASE + 0x0142 + (CHAN) * 0x10)
#define ESR_RXTX_TUNING3_H(CHAN) (ESR_BASE + 0x0142 + (CHAN) * 0x10)
#define ESR2_TI_PLL_TX_CFG_L(CHAN) (ESR2_BASE + 0x100 + (CHAN) * 4)
#define ESR2_TI_PLL_TX_CFG_H(CHAN) (ESR2_BASE + 0x101 + (CHAN) * 4)
#define ESR2_TI_PLL_TX_STS_L(CHAN) (ESR2_BASE + 0x102 + (CHAN) * 4)
#define ESR2_TI_PLL_TX_STS_H(CHAN) (ESR2_BASE + 0x103 + (CHAN) * 4)
#define ESR2_TI_PLL_RX_CFG_L(CHAN) (ESR2_BASE + 0x120 + (CHAN) * 4)
#define ESR2_TI_PLL_RX_CFG_H(CHAN) (ESR2_BASE + 0x121 + (CHAN) * 4)
#define ESR2_TI_PLL_RX_STS_L(CHAN) (ESR2_BASE + 0x122 + (CHAN) * 4)
#define ESR2_TI_PLL_RX_STS_H(CHAN) (ESR2_BASE + 0x123 + (CHAN) * 4)
#define TXC_DMA_MAX(CHAN) (FZC_TXC + 0x00000UL + (CHAN)*0x1000UL)
#define TXC_DMA_MAX_LEN(CHAN) (FZC_TXC + 0x00008UL + (CHAN)*0x1000UL)
#define LDN_RXDMA(CHAN) (0 + (CHAN))
#define LDN_TXDMA(CHAN) (32 + (CHAN))
#define ESR_RXTX_CTRL_L(CHAN) (ESR_BASE + 0x0080 + (CHAN) * 0x10)
#define ESR_RXTX_CTRL_H(CHAN) (ESR_BASE + 0x0081 + (CHAN) * 0x10)
#define ESR_RXTX_TUNING_L(CHAN) (ESR_BASE + 0x0082 + (CHAN) * 0x10)
CHAN(2432, 4),
CHAN(2437, 5),
CHAN(2442, 6),
CHAN(2447, 7),
CHAN(2452, 8),
CHAN(2457, 9),
CHAN(2462, 10),
CHAN(2467, 11),
CHAN(2472, 12),
CHAN(2484, 13),
CHAN(4920, 14),
CHAN(4940, 15),
CHAN(4960, 16),
CHAN(4980, 17),
CHAN(5040, 18),
CHAN(5060, 19),
CHAN(5080, 20),
CHAN(5180, 21),
CHAN(5200, 22),
CHAN(5220, 23),
CHAN(5240, 24),
CHAN(5260, 25),
CHAN(5280, 26),
CHAN(5300, 27),
CHAN(5320, 28),
CHAN(5500, 29),
CHAN(5520, 30),
CHAN(5540, 31),
CHAN(5560, 32),
CHAN(5580, 33),
CHAN(5600, 34),
CHAN(5620, 35),
CHAN(5640, 36),
CHAN(5660, 37),
CHAN(5680, 38),
CHAN(5700, 39),
CHAN(5745, 40),
CHAN(5765, 41),
CHAN(5785, 42),
CHAN(5805, 43),
CHAN(5825, 44),
CHAN(5170, 45),
CHAN(5190, 46),
CHAN(5210, 47),
CHAN(5230, 48),
CHAN(2412, 0),
CHAN(2417, 1),
CHAN(2422, 2),
CHAN(2427, 3),