enet_write
enet_write(enet, offset, val);
enet_write(enet, ENET_UNIMAC + offset, value);
enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_INT_MASK, ENET_DMA_INT_DEFAULTS);
enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_INT_MASK, 0);
enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_INT_STAT, ENET_DMA_INT_DEFAULTS);
enet_write(enet, rings[i]->cfg_block + ENET_DMA_CH_CFG, 0);
enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_BASE_DESC_PTR, 0);
enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_STATE_DATA, 0);
enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_DESC_LEN_STATUS, 0);
enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_DESC_BASE_BUFPTR, 0);
enet_write(enet, ENET_DMA_CTRL_CHANNEL_RESET, BIT(reset_channel * 2 + reset_subch));
enet_write(enet, ENET_DMA_CTRL_CHANNEL_RESET, 0);
enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, 0);
enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_MAX_BURST, ENET_DMA_MAX_BURST_LEN);
enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_INT_MASK, 0);
enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_BASE_DESC_PTR,
enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE);
enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, 0);