enet_dmas_writel
enet_dmas_writel(priv, priv->rx_desc_dma,
enet_dmas_writel(priv, priv->tx_desc_dma,
enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->rx_chan);
enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->tx_chan);
enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->rx_chan);
enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->tx_chan);
enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->rx_chan);
enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->tx_chan);
enet_dmas_writel(priv, priv->rx_desc_dma,
enet_dmas_writel(priv, priv->tx_desc_dma,
enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->rx_chan);
enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->tx_chan);
enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->rx_chan);
enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->tx_chan);
enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->rx_chan);
enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->tx_chan);