encx24j600_write_reg
encx24j600_write_reg(priv, MABBIPG, 0x15);
encx24j600_write_reg(priv, MABBIPG, 0x12);
encx24j600_write_reg(priv, MACLCON, 0x370f);
encx24j600_write_reg(priv, ERXRDPT, priv->next_packet);
encx24j600_write_reg(priv, ERXTAIL, newrxtail);
encx24j600_write_reg(priv, EUDAST, EUDAST_TEST_VAL);
encx24j600_write_reg(priv, EGPWRPT, ENC_TX_BUF_START);
encx24j600_write_reg(priv, ERXST, ENC_RX_BUF_START);
encx24j600_write_reg(priv, ERXRDPT, ENC_RX_BUF_START);
encx24j600_write_reg(priv, ERXTAIL, ENC_SRAM_SIZE - 2);
encx24j600_write_reg(priv, EUDAST, ENC_SRAM_SIZE);
encx24j600_write_reg(priv, EUDAND, ENC_SRAM_SIZE + 1);
encx24j600_write_reg(priv, MAMXFL, MAX_FRAMELEN);
encx24j600_write_reg(priv, ERXFCON, UCEN | MCEN | NOTMEEN);
encx24j600_write_reg(priv, ERXFCON, UCEN | CRCEN | BCEN | MCEN);
encx24j600_write_reg(priv, ERXFCON, UCEN | CRCEN | BCEN);
encx24j600_write_reg(priv, MACON1, 0x9);
encx24j600_write_reg(priv, MAIPG, 0x0c12);
encx24j600_write_reg(priv, MAMXFL, MAX_FRAMELEN);
encx24j600_write_reg(priv, EIE, (PCFULIE | RXABTIE | TXABTIE | TXIE |
encx24j600_write_reg(priv, EIE, 0);
encx24j600_write_reg(priv, MAADR3, (dev->dev_addr[4] |
encx24j600_write_reg(priv, MAADR2, (dev->dev_addr[2] |
encx24j600_write_reg(priv, MAADR1, (dev->dev_addr[0] |
encx24j600_write_reg(priv, EGPWRPT, ENC_TX_BUF_START);
encx24j600_write_reg(priv, ETXST, ENC_TX_BUF_START);
encx24j600_write_reg(priv, ETXLEN, priv->tx_skb->len);