enable_clock
enable_clock(dev, *con_id);
enable_clock(dev, NULL);
.enable_clock = tegra20_enable_cpu_clock,
.enable_clock = tegra30_enable_cpu_clock,
crt->base.enable_clock = hsw_ddi_enable_clock;
if (encoder->enable_clock)
encoder->enable_clock(encoder, crtc_state);
encoder->enable_clock = intel_mtl_pll_enable_clock;
encoder->enable_clock = intel_mtl_pll_enable_clock;
encoder->enable_clock = intel_mpllb_enable;
encoder->enable_clock = adls_ddi_enable_clock;
encoder->enable_clock = rkl_ddi_enable_clock;
encoder->enable_clock = dg1_ddi_enable_clock;
encoder->enable_clock = jsl_ddi_tc_enable_clock;
encoder->enable_clock = icl_ddi_combo_enable_clock;
encoder->enable_clock = icl_ddi_tc_enable_clock;
encoder->enable_clock = icl_ddi_combo_enable_clock;
encoder->enable_clock = skl_ddi_enable_clock;
encoder->enable_clock = hsw_ddi_enable_clock;
void (*enable_clock)(struct intel_encoder *encoder,
drvdata->enable_clock = devm_clk_get(dev, NULL);
if (IS_ERR(drvdata->enable_clock)) {
return PTR_ERR(drvdata->enable_clock);
struct clk *enable_clock;
ret = clk_prepare_enable(priv->enable_clock);
clk_disable_unprepare(priv->enable_clock);
void (*enable_clock)(u32 cpu);
if (WARN_ON(!tegra_cpu_car_ops->enable_clock))
tegra_cpu_car_ops->enable_clock(cpu);