event_ctl
return idx * 8 + box->pmu->type->event_ctl;
return idx * 4 + box->pmu->type->event_ctl;
return box->pmu->type->event_ctl +
unsigned event_ctl;
hwc->config_base = box_ctl + box->pmu->type->event_ctl + hwc->idx;
uncore->event_ctl = (unsigned int)type->ctl_offset;
.event_ctl = NHMEX_R_MSR_PMON_CTL0,
.event_ctl = NHMEX_U_MSR_PMON_EV_SEL,
.event_ctl = NHMEX_C0_MSR_PMON_EV_SEL0,
.event_ctl = NHMEX_W_MSR_PMON_CNT0,
.event_ctl = NHMEX_B0_MSR_PMON_CTL0,
.event_ctl = NHMEX_S0_MSR_PMON_CTL0,
.event_ctl = NHMEX_M0_MSR_PMU_CTL0,
.event_ctl = NHM_UNC_PERFEVTSEL0,
.event_ctl = ADL_UNCORE_IMC_CTRL,
.event_ctl = LNL_UNCORE_HBO_CTRL,
.event_ctl = LNL_UNCORE_SNCU_CTRL,
.event_ctl = PTL_UNC_IA_CORE_BRIDGE_PERFEVTSEL0,
.event_ctl = PTL_UNC_SANTA_CTRL0,
mtl_uncore_cbox.event_ctl = NVL_UNC_CBOX_PERFEVTSEL0;
ptl_uncore_santa.event_ctl = NVL_UNC_SANTA_CTRL0;
.event_ctl = SNB_UNC_CBO_0_PERFEVTSEL0,
.event_ctl = SNB_UNC_ARB_PERFEVTSEL0,
.event_ctl = SNB_UNC_CBO_0_PERFEVTSEL0,
.event_ctl = SNB_UNC_CBO_0_PERFEVTSEL0,
.event_ctl = ICL_UNC_ARB_PERFEVTSEL,
.event_ctl = ADL_UNC_CBO_0_PERFEVTSEL0,
.event_ctl = ADL_UNC_ARB_PERFEVTSEL0,
.event_ctl = MTL_UNC_CBO_0_PERFEVTSEL0,
.event_ctl = MTL_UNC_HAC_ARB_CTRL,
.event_ctl = MTL_UNC_ARB_CTRL,
.event_ctl = MTL_UNC_HBO_CTRL,
.event_ctl = SNBEP_C0_MSR_PMON_CTL0,
.event_ctl = SNBEP_PCU_MSR_PMON_CTL0,
.event_ctl = SNBEP_PCI_PMON_CTL0, \
.event_ctl = SNBEP_PCI_PMON_CTL0,
.event_ctl = SNBEP_PCI_PMON_CTL0, \
.event_ctl = SNBEP_U_MSR_PMON_CTL0,
.event_ctl = SNBEP_C0_MSR_PMON_CTL0,
.event_ctl = SNBEP_PCU_MSR_PMON_CTL0,
.event_ctl = SNBEP_PCI_PMON_CTL0,
.event_ctl = HSWEP_U_MSR_PMON_CTL0,
.event_ctl = HSWEP_C0_MSR_PMON_CTL0,
.event_ctl = HSWEP_PCU_MSR_PMON_CTL0,
.event_ctl = KNL_UCLK_MSR_PMON_CTL0,
.event_ctl = KNL_MC0_CH0_MSR_PMON_CTL0,
.event_ctl = KNL_UCLK_MSR_PMON_CTL0,
.event_ctl = KNL_EDC0_ECLK_MSR_PMON_CTL0,
.event_ctl = SNBEP_PCI_PMON_CTL0,
.event_ctl = HSWEP_U_MSR_PMON_CTL0,
.event_ctl = HSWEP_C0_MSR_PMON_CTL0,
.event_ctl = HSWEP_S0_MSR_PMON_CTL0,
.event_ctl = HSWEP_PCU_MSR_PMON_CTL0,
.event_ctl = SNBEP_PCI_PMON_CTL0,
.event_ctl = HSWEP_U_MSR_PMON_CTL0,
.event_ctl = HSWEP_C0_MSR_PMON_CTL0,
.event_ctl = HSWEP_S0_MSR_PMON_CTL0,
.event_ctl = SNBEP_PCI_PMON_CTL0,
.event_ctl = HSWEP_U_MSR_PMON_CTL0,
.event_ctl = HSWEP_C0_MSR_PMON_CTL0,
.event_ctl = SKX_IIO0_MSR_PMON_CTL0,
.event_ctl = SKX_IRP0_MSR_PMON_CTL0,
.event_ctl = HSWEP_PCU_MSR_PMON_CTL0,
.event_ctl = SNBEP_PCI_PMON_CTL0,
.event_ctl = SKX_UPI_PCI_PMON_CTL0,
.event_ctl = SKX_M2M_PCI_PMON_CTL0,
.event_ctl = SNBEP_PCI_PMON_CTL0,
.event_ctl = SNBEP_PCI_PMON_CTL0,
.event_ctl = SNR_U_MSR_PMON_CTL0,
.event_ctl = SNR_CHA_MSR_PMON_CTL0,
.event_ctl = SNR_IIO_MSR_PMON_CTL0,
.event_ctl = SNR_IRP0_MSR_PMON_CTL0,
.event_ctl = SNR_M2PCIE_MSR_PMON_CTL0,
.event_ctl = SNR_PCU_MSR_PMON_CTL0,
.event_ctl = SNR_M2M_PCI_PMON_CTL0,
.event_ctl = SNR_PCIE3_PCI_PMON_CTL0,
.event_ctl = SNR_IMC_MMIO_PMON_CTL0,
.event_ctl = ICX_C34_MSR_PMON_CTL0,
.event_ctl = ICX_IIO_MSR_PMON_CTL0,
.event_ctl = ICX_IRP0_MSR_PMON_CTL0,
.event_ctl = ICX_M2PCIE_MSR_PMON_CTL0,
.event_ctl = SNR_M2M_PCI_PMON_CTL0,
.event_ctl = ICX_UPI_PCI_PMON_CTL0,
.event_ctl = ICX_M3UPI_PCI_PMON_CTL0,
.event_ctl = SNR_IMC_MMIO_PMON_CTL0,
.event_ctl = ICX_UPI_PCI_PMON_CTL0 - ICX_UPI_PCI_PMON_BOX_CTL,
.event_ctl = ICX_M3UPI_PCI_PMON_CTL0 - ICX_M3UPI_PCI_PMON_BOX_CTL,
.event_ctl = SNBEP_U_MSR_PMON_CTL0,
ret = event_ctl(stdev, &ctl);
ret = event_ctl(stdev, &ctl);