ethoc_read
(ethoc_read(priv, MIIMODER) & MIIMODER_NOPRE) |
bd->stat = ethoc_read(dev, offset + 0);
bd->addr = ethoc_read(dev, offset + 4);
u32 imask = ethoc_read(dev, INT_MASK);
u32 imask = ethoc_read(dev, INT_MASK);
u32 mode = ethoc_read(dev, MODER);
u32 mode = ethoc_read(dev, MODER);
mode = ethoc_read(dev, MODER);
mode = ethoc_read(dev, MODER);
mask = ethoc_read(priv, INT_MASK);
pending = ethoc_read(priv, INT_SOURCE);
reg = ethoc_read(priv, MAC_ADDR0);
reg = ethoc_read(priv, MAC_ADDR1);
u32 status = ethoc_read(priv, MIISTATUS);
u32 data = ethoc_read(priv, MIIRX_DATA);
u32 stat = ethoc_read(priv, MIISTATUS);
mode = ethoc_read(priv, MODER);
u32 mode = ethoc_read(priv, MODER);
u32 pending = ethoc_read(priv, INT_SOURCE);
regs_buff[i] = ethoc_read(priv, i * sizeof(u32));