ef4_mdio_read
devs1 = ef4_mdio_read(efx, probe_mmd, MDIO_DEVS1);
devs2 = ef4_mdio_read(efx, probe_mmd, MDIO_DEVS2);
int stat = ef4_mdio_read(efx, mmd, MDIO_STAT1);
reg = ef4_mdio_read(efx, MDIO_MMD_AN, MDIO_CTRL1);
ef4_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_LPA));
physid1 = ef4_mdio_read(efx, devad, MDIO_DEVID1);
physid2 = ef4_mdio_read(efx, devad, MDIO_DEVID2);
ctrl = ef4_mdio_read(port, mmd, MDIO_CTRL1);
status = ef4_mdio_read(efx, mmd, MDIO_STAT2);
stat = ef4_mdio_read(efx, mmd, MDIO_CTRL1);
u16 id_low = ef4_mdio_read(efx, mmd, MDIO_DEVID2);
u16 id_hi = ef4_mdio_read(efx, mmd, MDIO_DEVID1);
lane_status = ef4_mdio_read(efx, MDIO_MMD_PHYXS,
reg = ef4_mdio_read(efx, MDIO_MMD_PCS, PCS_UC8051_STATUS_REG);
firmware_id[i] = ef4_mdio_read(efx, MDIO_MMD_PCS,
reg = ef4_mdio_read(efx, 1, 0xc319);
rc = ef4_mdio_read(efx, mmd, reg_base + ee->offset + i);
reg = ef4_mdio_read(efx, MDIO_MMD_PCS, PCS_FW_HEARTBEAT_REG);
reg = ef4_mdio_read(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG);
reg = ef4_mdio_read(efx, MDIO_MMD_AN, MDIO_STAT1);
reg = ef4_mdio_read(efx, MDIO_MMD_PMAPMD,
reg = ef4_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL);
reg = ef4_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_10GBT_STAT);
ctrl = ef4_mdio_read(efx, MDIO_MMD_PCS, TXC_MTDIABLO_CTRL);
bctl = ef4_mdio_read(efx, mmd, TXC_BIST_CTL);
int count = ef4_mdio_read(efx, mmd, TXC_BIST_RX0ERRCNT + lane);
count = ef4_mdio_read(efx, mmd, TXC_BIST_RX0FRMCNT + lane);
mctrl = ef4_mdio_read(efx, MDIO_MMD_PHYXS, TXC_MRGS_CTL);
int ctl = ef4_mdio_read(efx, mmd, TXC_GLRGS_GLCMD);
int txctl = ef4_mdio_read(efx, mmd, TXC_ALRGS_ATXCTL);
int rxctl = ef4_mdio_read(efx, mmd, TXC_ALRGS_ARXCTL);
int val = ef4_mdio_read(efx, mmd, TXC_GLRGS_GLCMD);
val = ef4_mdio_read(efx, mmd, TXC_GLRGS_GLCMD);