eeh_ops
extern struct eeh_ops *eeh_ops;
int __init eeh_init(struct eeh_ops *ops);
edev = eeh_ops->probe(dev);
struct eeh_ops *eeh_ops = NULL;
ret = eeh_ops->get_state(pe, NULL);
if (!eeh_ops || !eeh_ops->set_option) {
if (!eeh_ops || !eeh_ops->get_state)
result = eeh_ops->get_state(pe, NULL);
if (!eeh_ops || !eeh_ops->set_option || !eeh_ops->reset)
ret = eeh_ops->reset(pe, option);
eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);
ret = eeh_ops->reset(pe, option);
ret = eeh_ops->configure_bridge(pe);
if (!eeh_ops || !eeh_ops->err_inject)
return eeh_ops->err_inject(pe, type, func, addr, mask);
eeh_ops->read_config(edev, PCI_VENDOR_ID, 4, &cfg);
eeh_ops->read_config(edev, PCI_COMMAND, 4, &cfg);
eeh_ops->read_config(edev, PCI_SEC_STATUS, 2, &cfg);
eeh_ops->read_config(edev, PCI_BRIDGE_CONTROL, 2, &cfg);
eeh_ops->read_config(edev, cap, 4, &cfg);
eeh_ops->read_config(edev, cap+4, 4, &cfg);
eeh_ops->read_config(edev, cap+4*i, 4, &cfg);
eeh_ops->read_config(edev, cap+4*i, 4, &cfg);
eeh_ops->configure_bridge(pe);
eeh_ops->get_log(pe, severity, pci_regs_buf, loglen);
ret = eeh_ops->get_state(phb_pe, NULL);
ret = eeh_ops->get_state(pe, NULL);
ret = eeh_ops->get_state(parent_pe, NULL);
rc = eeh_ops->get_state(pe, NULL);
rc = eeh_ops->set_option(pe, function);
if (eeh_ops->restore_config)
eeh_ops->restore_config(edev);
eeh_ops->reset(pe, EEH_RESET_DEACTIVATE);
eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);
eeh_ops->reset(pe, EEH_RESET_HOT);
eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);
eeh_ops->reset(pe, EEH_RESET_FUNDAMENTAL);
state = eeh_ops->get_state(pe, NULL);
eeh_ops->read_config(edev, i * 4, 4, &edev->config_space[i]);
int eeh_init(struct eeh_ops *ops)
if (WARN_ON(eeh_ops))
eeh_ops = ops;
rc = eeh_ops->next_error(&pe);
if (eeh_ops->notify_resume)
eeh_ops->notify_resume(edev);
eeh_ops->configure_bridge(pe);
ret = eeh_ops->get_state(pe, &mwait);
eeh_ops->read_config(edev, cap + PCI_EXP_SLTSTA, 2, &val);
eeh_ops->read_config(edev, cap + PCI_EXP_SLTCAP, 2, &val);
eeh_ops->read_config(edev, cap + PCI_EXP_SLTCTL, 2, &val);
eeh_ops->write_config(edev, cap + PCI_EXP_SLTCTL, 2, val);
eeh_ops->read_config(edev, cap + PCI_EXP_LNKCTL, 2, &val);
eeh_ops->write_config(edev, cap + PCI_EXP_LNKCTL, 2, val);
eeh_ops->read_config(edev, cap + PCI_EXP_LNKSTA, 2, &val);
eeh_ops->write_config(edev, i*4, 4, edev->config_space[i]);
eeh_ops->write_config(edev, 14*4, 4, edev->config_space[14]);
eeh_ops->write_config(edev, PCI_CACHE_LINE_SIZE, 1,
eeh_ops->write_config(edev, PCI_LATENCY_TIMER, 1,
eeh_ops->write_config(edev, 15*4, 4, edev->config_space[15]);
eeh_ops->write_config(edev, PCI_COMMAND, 4, edev->config_space[1] |
eeh_ops->write_config(edev, i*4, 4, edev->config_space[i]);
eeh_ops->write_config(edev, 12*4, 4, edev->config_space[12]);
eeh_ops->write_config(edev, PCI_CACHE_LINE_SIZE, 1,
eeh_ops->write_config(edev, PCI_LATENCY_TIMER, 1,
eeh_ops->write_config(edev, 15*4, 4, edev->config_space[15]);
eeh_ops->read_config(edev, PCI_COMMAND, 4, &cmd);
eeh_ops->write_config(edev, PCI_COMMAND, 4, cmd);
if (eeh_ops->restore_config)
eeh_ops->restore_config(edev);
if (!edev || !edev->pe || !eeh_ops->notify_resume)
if (eeh_ops->notify_resume(edev))
state = eeh_ops->get_state(edev->pe, NULL);
ret = eeh_ops->get_state(dev_pe, NULL);
state = eeh_ops->get_state(parent_pe, NULL);
static struct eeh_ops pnv_eeh_ops = {
if (!eeh_ops || !eeh_ops->err_inject)
eeh_ops->read_config(edev, aer + PCI_ERR_UNCOR_MASK,
eeh_ops->write_config(edev, aer + PCI_ERR_UNCOR_MASK,
eeh_ops->read_config(edev, PCI_BRIDGE_CONTROL, 2, &ctrl);
eeh_ops->write_config(edev, PCI_BRIDGE_CONTROL, 2, ctrl);
eeh_ops->read_config(edev, PCI_BRIDGE_CONTROL, 2, &ctrl);
eeh_ops->write_config(edev, PCI_BRIDGE_CONTROL, 2, ctrl);
eeh_ops->read_config(edev, aer + PCI_ERR_UNCOR_MASK,
eeh_ops->write_config(edev, aer + PCI_ERR_UNCOR_MASK,
eeh_ops->read_config(edev, pos, 2, &status);
eeh_ops->read_config(edev, edev->pcie_cap + PCI_EXP_DEVCAP, 4, ®);
eeh_ops->read_config(edev, edev->pcie_cap + PCI_EXP_DEVCTL,
eeh_ops->write_config(edev, edev->pcie_cap + PCI_EXP_DEVCTL,
eeh_ops->read_config(edev, edev->pcie_cap + PCI_EXP_DEVCTL,
eeh_ops->write_config(edev, edev->pcie_cap + PCI_EXP_DEVCTL,
ret = eeh_ops->err_inject(pe, type, func, addr, mask);
eeh_ops->read_config(edev, edev->af_cap + PCI_AF_CAP, 1, &cap);
eeh_ops->write_config(edev, edev->af_cap + PCI_AF_CTRL,
eeh_ops->write_config(edev, edev->af_cap + PCI_AF_CTRL, 1, 0);
ret = eeh_ops->set_option(&pe, EEH_OPT_ENABLE);
static struct eeh_ops pseries_eeh_ops = {