Symbol: eeh_ops
arch/powerpc/include/asm/eeh.h
235
extern struct eeh_ops *eeh_ops;
arch/powerpc/include/asm/eeh.h
296
int __init eeh_init(struct eeh_ops *ops);
arch/powerpc/kernel/eeh.c
1022
edev = eeh_ops->probe(dev);
arch/powerpc/kernel/eeh.c
109
struct eeh_ops *eeh_ops = NULL;
arch/powerpc/kernel/eeh.c
1160
ret = eeh_ops->get_state(pe, NULL);
arch/powerpc/kernel/eeh.c
1336
if (!eeh_ops || !eeh_ops->set_option) {
arch/powerpc/kernel/eeh.c
1369
if (!eeh_ops || !eeh_ops->get_state)
arch/powerpc/kernel/eeh.c
1383
result = eeh_ops->get_state(pe, NULL);
arch/powerpc/kernel/eeh.c
1458
if (!eeh_ops || !eeh_ops->set_option || !eeh_ops->reset)
arch/powerpc/kernel/eeh.c
1463
ret = eeh_ops->reset(pe, option);
arch/powerpc/kernel/eeh.c
1477
eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);
arch/powerpc/kernel/eeh.c
1480
ret = eeh_ops->reset(pe, option);
arch/powerpc/kernel/eeh.c
1508
ret = eeh_ops->configure_bridge(pe);
arch/powerpc/kernel/eeh.c
1534
if (!eeh_ops || !eeh_ops->err_inject)
arch/powerpc/kernel/eeh.c
1541
return eeh_ops->err_inject(pe, type, func, addr, mask);
arch/powerpc/kernel/eeh.c
182
eeh_ops->read_config(edev, PCI_VENDOR_ID, 4, &cfg);
arch/powerpc/kernel/eeh.c
186
eeh_ops->read_config(edev, PCI_COMMAND, 4, &cfg);
arch/powerpc/kernel/eeh.c
192
eeh_ops->read_config(edev, PCI_SEC_STATUS, 2, &cfg);
arch/powerpc/kernel/eeh.c
196
eeh_ops->read_config(edev, PCI_BRIDGE_CONTROL, 2, &cfg);
arch/powerpc/kernel/eeh.c
204
eeh_ops->read_config(edev, cap, 4, &cfg);
arch/powerpc/kernel/eeh.c
208
eeh_ops->read_config(edev, cap+4, 4, &cfg);
arch/powerpc/kernel/eeh.c
220
eeh_ops->read_config(edev, cap+4*i, 4, &cfg);
arch/powerpc/kernel/eeh.c
247
eeh_ops->read_config(edev, cap+4*i, 4, &cfg);
arch/powerpc/kernel/eeh.c
328
eeh_ops->configure_bridge(pe);
arch/powerpc/kernel/eeh.c
337
eeh_ops->get_log(pe, severity, pci_regs_buf, loglen);
arch/powerpc/kernel/eeh.c
382
ret = eeh_ops->get_state(phb_pe, NULL);
arch/powerpc/kernel/eeh.c
502
ret = eeh_ops->get_state(pe, NULL);
arch/powerpc/kernel/eeh.c
539
ret = eeh_ops->get_state(parent_pe, NULL);
arch/powerpc/kernel/eeh.c
647
rc = eeh_ops->get_state(pe, NULL);
arch/powerpc/kernel/eeh.c
662
rc = eeh_ops->set_option(pe, function);
arch/powerpc/kernel/eeh.c
719
if (eeh_ops->restore_config)
arch/powerpc/kernel/eeh.c
720
eeh_ops->restore_config(edev);
arch/powerpc/kernel/eeh.c
748
eeh_ops->reset(pe, EEH_RESET_DEACTIVATE);
arch/powerpc/kernel/eeh.c
758
eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);
arch/powerpc/kernel/eeh.c
762
eeh_ops->reset(pe, EEH_RESET_HOT);
arch/powerpc/kernel/eeh.c
767
eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);
arch/powerpc/kernel/eeh.c
771
eeh_ops->reset(pe, EEH_RESET_FUNDAMENTAL);
arch/powerpc/kernel/eeh.c
808
state = eeh_ops->get_state(pe, NULL);
arch/powerpc/kernel/eeh.c
910
eeh_ops->read_config(edev, i * 4, 4, &edev->config_space[i]);
arch/powerpc/kernel/eeh.c
963
int eeh_init(struct eeh_ops *ops)
arch/powerpc/kernel/eeh.c
969
if (WARN_ON(eeh_ops))
arch/powerpc/kernel/eeh.c
973
eeh_ops = ops;
arch/powerpc/kernel/eeh_driver.c
1150
rc = eeh_ops->next_error(&pe);
arch/powerpc/kernel/eeh_driver.c
434
if (eeh_ops->notify_resume)
arch/powerpc/kernel/eeh_driver.c
435
eeh_ops->notify_resume(edev);
arch/powerpc/kernel/eeh_driver.c
674
eeh_ops->configure_bridge(pe);
arch/powerpc/kernel/eeh_pe.c
124
ret = eeh_ops->get_state(pe, &mwait);
arch/powerpc/kernel/eeh_pe.c
649
eeh_ops->read_config(edev, cap + PCI_EXP_SLTSTA, 2, &val);
arch/powerpc/kernel/eeh_pe.c
656
eeh_ops->read_config(edev, cap + PCI_EXP_SLTCAP, 2, &val);
arch/powerpc/kernel/eeh_pe.c
658
eeh_ops->read_config(edev, cap + PCI_EXP_SLTCTL, 2, &val);
arch/powerpc/kernel/eeh_pe.c
663
eeh_ops->write_config(edev, cap + PCI_EXP_SLTCTL, 2, val);
arch/powerpc/kernel/eeh_pe.c
669
eeh_ops->read_config(edev, cap + PCI_EXP_LNKCTL, 2, &val);
arch/powerpc/kernel/eeh_pe.c
671
eeh_ops->write_config(edev, cap + PCI_EXP_LNKCTL, 2, val);
arch/powerpc/kernel/eeh_pe.c
688
eeh_ops->read_config(edev, cap + PCI_EXP_LNKSTA, 2, &val);
arch/powerpc/kernel/eeh_pe.c
712
eeh_ops->write_config(edev, i*4, 4, edev->config_space[i]);
arch/powerpc/kernel/eeh_pe.c
714
eeh_ops->write_config(edev, 14*4, 4, edev->config_space[14]);
arch/powerpc/kernel/eeh_pe.c
717
eeh_ops->write_config(edev, PCI_CACHE_LINE_SIZE, 1,
arch/powerpc/kernel/eeh_pe.c
719
eeh_ops->write_config(edev, PCI_LATENCY_TIMER, 1,
arch/powerpc/kernel/eeh_pe.c
722
eeh_ops->write_config(edev, 15*4, 4, edev->config_space[15]);
arch/powerpc/kernel/eeh_pe.c
725
eeh_ops->write_config(edev, PCI_COMMAND, 4, edev->config_space[1] |
arch/powerpc/kernel/eeh_pe.c
738
eeh_ops->write_config(edev, i*4, 4, edev->config_space[i]);
arch/powerpc/kernel/eeh_pe.c
740
eeh_ops->write_config(edev, 12*4, 4, edev->config_space[12]);
arch/powerpc/kernel/eeh_pe.c
742
eeh_ops->write_config(edev, PCI_CACHE_LINE_SIZE, 1,
arch/powerpc/kernel/eeh_pe.c
744
eeh_ops->write_config(edev, PCI_LATENCY_TIMER, 1,
arch/powerpc/kernel/eeh_pe.c
748
eeh_ops->write_config(edev, 15*4, 4, edev->config_space[15]);
arch/powerpc/kernel/eeh_pe.c
754
eeh_ops->read_config(edev, PCI_COMMAND, 4, &cmd);
arch/powerpc/kernel/eeh_pe.c
763
eeh_ops->write_config(edev, PCI_COMMAND, 4, cmd);
arch/powerpc/kernel/eeh_pe.c
783
if (eeh_ops->restore_config)
arch/powerpc/kernel/eeh_pe.c
784
eeh_ops->restore_config(edev);
arch/powerpc/kernel/eeh_sysfs.c
100
if (!edev || !edev->pe || !eeh_ops->notify_resume)
arch/powerpc/kernel/eeh_sysfs.c
103
if (eeh_ops->notify_resume(edev))
arch/powerpc/kernel/eeh_sysfs.c
52
state = eeh_ops->get_state(edev->pe, NULL);
arch/powerpc/platforms/powernv/eeh-powernv.c
1377
ret = eeh_ops->get_state(dev_pe, NULL);
arch/powerpc/platforms/powernv/eeh-powernv.c
1573
state = eeh_ops->get_state(parent_pe, NULL);
arch/powerpc/platforms/powernv/eeh-powernv.c
1626
static struct eeh_ops pnv_eeh_ops = {
arch/powerpc/platforms/powernv/eeh-powernv.c
76
if (!eeh_ops || !eeh_ops->err_inject)
arch/powerpc/platforms/powernv/eeh-powernv.c
817
eeh_ops->read_config(edev, aer + PCI_ERR_UNCOR_MASK,
arch/powerpc/platforms/powernv/eeh-powernv.c
820
eeh_ops->write_config(edev, aer + PCI_ERR_UNCOR_MASK,
arch/powerpc/platforms/powernv/eeh-powernv.c
824
eeh_ops->read_config(edev, PCI_BRIDGE_CONTROL, 2, &ctrl);
arch/powerpc/platforms/powernv/eeh-powernv.c
826
eeh_ops->write_config(edev, PCI_BRIDGE_CONTROL, 2, ctrl);
arch/powerpc/platforms/powernv/eeh-powernv.c
831
eeh_ops->read_config(edev, PCI_BRIDGE_CONTROL, 2, &ctrl);
arch/powerpc/platforms/powernv/eeh-powernv.c
833
eeh_ops->write_config(edev, PCI_BRIDGE_CONTROL, 2, ctrl);
arch/powerpc/platforms/powernv/eeh-powernv.c
839
eeh_ops->read_config(edev, aer + PCI_ERR_UNCOR_MASK,
arch/powerpc/platforms/powernv/eeh-powernv.c
842
eeh_ops->write_config(edev, aer + PCI_ERR_UNCOR_MASK,
arch/powerpc/platforms/powernv/eeh-powernv.c
915
eeh_ops->read_config(edev, pos, 2, &status);
arch/powerpc/platforms/powernv/eeh-powernv.c
936
eeh_ops->read_config(edev, edev->pcie_cap + PCI_EXP_DEVCAP, 4, &reg);
arch/powerpc/platforms/powernv/eeh-powernv.c
946
eeh_ops->read_config(edev, edev->pcie_cap + PCI_EXP_DEVCTL,
arch/powerpc/platforms/powernv/eeh-powernv.c
949
eeh_ops->write_config(edev, edev->pcie_cap + PCI_EXP_DEVCTL,
arch/powerpc/platforms/powernv/eeh-powernv.c
954
eeh_ops->read_config(edev, edev->pcie_cap + PCI_EXP_DEVCTL,
arch/powerpc/platforms/powernv/eeh-powernv.c
957
eeh_ops->write_config(edev, edev->pcie_cap + PCI_EXP_DEVCTL,
arch/powerpc/platforms/powernv/eeh-powernv.c
96
ret = eeh_ops->err_inject(pe, type, func, addr, mask);
arch/powerpc/platforms/powernv/eeh-powernv.c
974
eeh_ops->read_config(edev, edev->af_cap + PCI_AF_CAP, 1, &cap);
arch/powerpc/platforms/powernv/eeh-powernv.c
989
eeh_ops->write_config(edev, edev->af_cap + PCI_AF_CTRL,
arch/powerpc/platforms/powernv/eeh-powernv.c
994
eeh_ops->write_config(edev, edev->af_cap + PCI_AF_CTRL, 1, 0);
arch/powerpc/platforms/pseries/eeh_pseries.c
438
ret = eeh_ops->set_option(&pe, EEH_OPT_ENABLE);
arch/powerpc/platforms/pseries/eeh_pseries.c
826
static struct eeh_ops pseries_eeh_ops = {